Add a parameter to the control the clock source option of the MMCM. If
the MMCM has only one clock source the CLKSEL pin will be tied to VDD.
The previous version added a redundant path between the CLKSEL port and
register map.
Explicitly select MIO 52 and 53 pins to be part of MDIO port.
MIO_52_PIN (MDIO 0 Clock, Output)
MIO_53_PIN (MDIO 0 Data, Input/Output)
After the tool version change, this pins where by default connected
as MIO GPIOs.
Explicitly disable the "Transfer Start Synchronisation Support"
since the sync lines are not connected in this project.
If the sync input line (s_axi_user[0] or fifo_wr_sync) are not connected,
Vivado 2017.4.1 no longer connects them to the defaultValue defined
in the axi_dmac ip (1). Instead he uses the defaulValue field defined
in the interface definition which in case of both interfaces is 0;
This module upscale an n*sample_width data bus into a 16 or 32*n data
bus. The samples are right aligned and supports offset binary or two's
complement data format.
The up_xfer_cntrl and up_xfer_status modules have its own constraints files
in library/xilinx/common. Each IP which has an instance of these
modules, have to use these constraints files.
The following IPs were modified:
- axi_adc_decimate
- axi_adc_trigger
- axi_dac_interpolate
- axi_logic_analyzer
Loop back the unused GPIO pins, and add all the SPI interface to system
wrapper instance.
The following system_top modules were changed:
- ad738x_fmc
- ad7616_sdz
- ad77681evb
- ad77681evb
- ad7768evb
- ad9739a_fmc
- ad9434
- adrv9739
- fmcadc5
- ad6676evb
- ad9265
- ad5766
- fmcomms5
- m2k
A couple of new parameters and new ports are missing in several
up_[adc|dac]_[common|channel] instance, and generates warnings. The rule of
thumb is to use full instantiations, defining all the existing parameter and
ports of the module.
Fix all the instantiation of up_[adc|dac]_[common|channel], by defining all its
parameters and ports.
The constraint where added to remove timing problems on the reset path.
The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.
Projects affected by this change:
- daq3
- adrv9739
- ad6676evb
- fmcadc5
- daq2/kcu105
- fmcadc2
- adrv9371x
- fmcomms11/zc706
- fmcjesdadc1
By default every base design has a SPI interface (hard or soft). In
case of soft IPs (xilinx), the input registers of the interface by default have
the IOB attribute set to TRUE. If the interface are not used, the tool will
generate a critical warning, stating that IOB registers are not connected to
an IO buffer.
The following constraints are disabling the above setup for every base
design, which using a soft SPI IP.
Laszlo Nagy
Istvan Csomortani
Rejeesh Kutty
Adrian Costina
AndreiGrozav