Rejeesh Kutty
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4927ca85c2
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projects- jesd-align port name change
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2015-05-20 14:24:26 -04:00 |
Adrian Costina
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e332fa01c8
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ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection
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2015-04-30 12:11:46 +03:00 |
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Adrian Costina
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037484e1d0
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usdrx1: Updated project to the latest framework
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2015-03-25 17:39:51 +02:00 |
Istvan Csomortani
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4ea86de4db
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usdrx1_zc706: Update interrupts.
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2014-11-27 14:03:54 +02:00 |
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Istvan Csomortani
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d1af4d2951
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usdrx1_fmc: Fix GT lane number definition.
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2014-11-27 14:03:10 +02:00 |
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Adrian Costina
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a0d27a117c
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usdrx1: Updated project with new synchronization mechanism. Fixed timing constraints
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2014-10-22 13:20:44 +03:00 |
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Istvan Csomortani
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17675863e0
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all_projects: Fix the interrupt connections to preserve IRQ layout
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2014-10-22 11:48:08 +03:00 |
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Adrian Costina
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8934a66013
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usdrx1: Update project so that the AD9671 cores can be synchronized
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2014-10-13 17:06:40 +03:00 |
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acostina
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296983707b
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usdrx1: Updated project to 2014.2
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2014-09-23 22:45:50 -04:00 |
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acostina
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5af2474d51
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usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
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2014-09-23 22:44:33 -04:00 |
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Adrian Costina
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bdf01738a1
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ultrasound: disconnected ADN4670 chips from SPI lines.
Connected everything to ground so that the the clock selected is 0 and all outputs are enabled
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2014-09-23 22:30:42 -04:00 |
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Adrian Costina
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d33fb07587
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usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32.
GPIOs for which the directions is known, have been specifically assigned.
The SPI clock has been changed to a lower frequency.
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2014-09-16 15:56:19 -04:00 |
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Adrian Costina
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a773cc4992
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usdrx1: updated project
ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
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2014-09-01 15:18:39 +03:00 |
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Adrian Costina
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6e444559b5
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usdrx1: global clock fix
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2014-06-10 18:09:49 +03:00 |
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Rejeesh Kutty
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96541f0a7f
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usdrx1: zc706 updated for usdrx1
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2014-04-10 11:05:13 -04:00 |
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Rejeesh Kutty
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6f36f74eea
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usdrx1: common board files
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2014-04-10 11:05:11 -04:00 |