Commit Graph

20 Commits (e8ff32d6df69276ea773921f7036314c1b50fe26)

Author SHA1 Message Date
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
Laszlo Nagy fa7c85a9eb all: Drive undriven input signals, complete interface
- connect unused GPIO inputs to loopback
- connect unconnected inputs to zero
- complete interface for system_wrapper instantiated in all system_top

fixes incomplet portlist WARNING [Synth 8-350]
fixes undriven inputs WARNING [Synth 8-3295]

The change excludes the generated system.v and Xilinx files.
2018-08-10 17:00:11 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani 98cf18dd51 daq3/zc706: Fix system_top instantiation
Delete used interrupt ports: the ps_intr_10 and ps_intr_11 is used by
the jesd cores.
2017-07-06 13:29:09 +01:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Rejeesh Kutty 862bd7ef2c daq3/zc706- xcvr changes 2016-11-23 15:02:20 -05:00
Istvan Csomortani bab9b2df0b daq3/zc706: Update project with the new transceiver modules 2016-10-05 17:41:25 +03:00
Rejeesh Kutty 6c0ad6ede8 daq3: bsplit/ccat -- removed 2015-07-15 13:05:53 -04:00
Rejeesh Kutty a6cae6b477 iobuf: do is a system verilog keyword 2015-05-21 14:06:17 -04:00
Rejeesh Kutty 275ce42bc9 daq3: 2014.4 updates 2015-03-19 12:45:55 -04:00
Istvan Csomortani 8121d11993 daq3_zc706: Connect PLDDR rst to external push button 2014-12-18 10:07:52 +02:00
Istvan Csomortani 090aed508e daq3_zc706: Delete trailing spaces from system_top 2014-12-18 10:06:29 +02:00
Rejeesh Kutty 1b4a4bc06e daq3: compilation fixes - latest changes 2014-12-08 14:51:52 -05:00
Rejeesh Kutty c375b5b26e daq3: vivado build 2014-10-06 10:34:02 -04:00
Rejeesh Kutty 525373fc04 daq3: daq2 copy 2014-10-06 10:34:00 -04:00