Commit Graph

5346 Commits (e773b2208743335894ccdff2ef0d928013edca3e)

Author SHA1 Message Date
Sergiu Arpadi c159909823 adrv9009_zu11eg_som: added i2s 2019-06-14 17:08:38 +03:00
Adrian Costina 9409df6a6f adrv9009_zu11eg: Initial commit
Observation and RX should never run at the same time.
Given that there is no FIFO on the RX and OBS paths, they will use the higheste performance HP ports, which are HP1 and HP2
2019-06-14 17:08:38 +03:00
Sergiu Arpadi 369974f2e7 axi_fan_control: updated ip
fixed tacho evaluation bug; updated fsm;
2019-06-14 17:08:38 +03:00
Istvan Csomortani 95afc461a6 fmcomms5: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 2e05b70d94 fmcomms11: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani dafc97f43a fmcjesdadc1: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 424abe0c02 adrv9009: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 5266d2ae88 ad6676evb: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 92a0e8eb1e util_adcfifo: Fix SDC cosntraints 2019-06-13 10:59:43 +03:00
Istvan Csomortani 78b14f9803 axi_ad9625: Fix the interface instance
The axi_ad9625_if does not have a DELAY_REFCLK_FREQUENCY parameter.
2019-06-13 10:59:43 +03:00
Istvan Csomortani 44a9331471 fmcomms2:fmcomms5: ZCU102 uses 500MHz IO delay clock 2019-06-11 18:13:06 +03:00
Istvan Csomortani 20b0c92a1f iodelay: Expose the REFCLK_FREQUENCY parameter 2019-06-11 18:13:06 +03:00
Istvan Csomortani 993497438b adi_project:adi_project_run: Check if $num_reg exist 2019-06-11 18:13:06 +03:00
Istvan Csomortani 896ea4925d adi_board: Fix ad_mem_hpx_interconnect proc
Make the lsearch command more robust.
2019-06-11 18:13:06 +03:00
Istvan Csomortani 019390f9bf block_design: Updates with new reset net variables 2019-06-11 18:13:06 +03:00
Istvan Csomortani 0e750bea42 adrv9009: Fix dma_clk tree 2019-06-11 18:13:06 +03:00
Istvan Csomortani 9072779e41 adrv9371x: Clean out system_db.tcl 2019-06-11 18:13:06 +03:00
Istvan Csomortani de510b45ab base: Add system_processor_rst for all the global clocks 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables
Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
Istvan Csomortani 20c714eccf common: Define three global clock nets
For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.

These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:

  - sys_cpu_clk     - 100MHz
  - sys_dma_clk     - 200MHz or 250Mhz
  - sys_iodelay_clk - 200MHz or 500Mhz
2019-06-11 18:13:06 +03:00
Istvan Csomortani c4c87c7c7a axi_ad9361: Fix the _hw.tcl script
This will fix an error introduced by 48d2c9d3 "axi_ad9361: Define a MIMO enabled
parameter"
2019-06-11 12:39:20 +01:00
Istvan Csomortani 93b2254ff5 axi_ad9361: Fix for 'Define a MIMO enabled parameter' 2019-06-10 14:48:17 +01:00
Istvan Csomortani 48d2c9d36f axi_ad9361: Define a MIMO enabled parameter
Define a MIMO_ENABLE parameter for the core, which will insert
and additional de-skew logic to prevent timing issues coming from
the clock skew differences of two or multiple AD9361.
2019-06-10 15:16:47 +03:00
Istvan Csomortani a4a9d0a19d fmcomms11/zc706: Relax core clock timing to 250MHz/125MHz 2019-06-10 11:23:41 +03:00
Istvan Csomortani 119fd0915a fmcomms11: Make the lane remapping after the link layer 2019-06-10 11:23:41 +03:00
Istvan Csomortani 58d55f61db fmcomms11: Add desciption how to swap memory resource for the FIFOs 2019-06-10 11:23:41 +03:00
Istvan Csomortani 5d80aa63b2 fmcomms11: Some cosmetic, no functional change 2019-06-10 11:23:41 +03:00
Istvan Csomortani 94dc848292 fmcomms11: Move the FIFO address variables into system_bd
These variables can vary in function of the available memory resources
of the FPGA carrier board.
2019-06-10 11:23:41 +03:00
Istvan Csomortani 559ae69b2b fmcomms11: Fix DAC data path
Fix the modification 68a5f2.
2019-06-10 11:23:41 +03:00
Istvan Csomortani d9230fdc5e fmcomms11: Connect DAC fifo bypass to a GPIO
GPIO[60] can be used to control the bypass line of the
util_dacfifo module.
2019-06-10 11:23:41 +03:00
Istvan Csomortani 70b7d69ff8 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
Laszlo Nagy 3bf120123b dac_fmc_ebz: update Makefiles 2019-06-06 11:45:05 +03:00
Laszlo Nagy 1541b918d8 dac_fmc_ebz: added README 2019-06-06 11:45:05 +03:00
Lars-Peter Clausen 6d31a437aa dac_fmc_ebz: Add initial Arria10 SoC support
Add support for the Arria 10 SoC development kit to the dac_fmc_ebz
project.

This allows to use the following FMC boards on the Arria 10 SoC development
Kit carrier:
  * AD9135-FMC-EBZ
  * AD9136-FMC-EBZ
  * AD9144-FMC-EBZ
  * AD9152-FMC-EBZ
  * AD9154-FMC-EBZ
  * AD9171-FMC-EBZ
  * AD9172-FMC-EBZ
  * AD9173-FMC-EBZ

Note that the board in its default configuration is not fully compatible with the
mentioned FMC boards and some slight re-work moving some 0 Ohm resistors is
required. The rework concerns the LA01 and LA05 pins, which by default are
not connected to the FPGA. The changes required are:

  LA01_P_CC
    R612: R0 -> DNI
    R610: DNI -> R0
  LA01_N_CC
    R613: R0 -> DNI
    R611: DNI -> R0
  LA05_P
    R621: R0 -> DNI
    R620: DNI -> R0
  LA05_N
    R633: R0 -> DNI
    R632: DNI -> R0

The main differences between AD9144-FMC-EBZ and AD9172-FMC-EBZ are:
  * The DAC txen signals are connected to different pins
  * The polarity of the spi_en signal is active low instead of active high
  * The maximum lane rate is up to 15.4 Gpbs

To accommodate this all 4 possible txen signals as well as the spi_en
signal are connected to GPIOs. Software can decide how to use them
depending on which FMC board is connected.

Note that each carrier has a maximum supported lane rate. Modes of the
AD9172 (and similar) that exceed the carrier specific limit can not be used
on that carrier. The limits are as following:
  * A10SoC: 14.2 Gbps
2019-06-06 11:45:05 +03:00
Lars-Peter Clausen c2c78b1b73 dac_fmc_ebz: Add initial ZCU102 and ZC706 carrier support
Add a generic project for the AD91xx-FMC-EBZ DAC boards connected to the
ZCU102 and ZC706 carrier boards.

The project is called dac_fmc_ebz as the intention is to support all DAC
FMC evaluation boards with this project since they are sufficiently similar
to be supported by the same design.
This project will successively extended to add support for more boards.

The desired DAC device and JESD operation mode must be selected from the following
file:
  ./common/config.tcl

This design can support the following FMC boards which are all pin
compatible:
  * AD9135-FMC-EBZ
  * AD9136-FMC-EBZ
  * AD9144-FMC-EBZ
  * AD9152-FMC-EBZ
  * AD9154-FMC-EBZ
  * AD916x-FMC-EBZ
  * AD9171-FMC-EBZ
  * AD9172-FMC-EBZ
  * AD9173-FMC-EBZ

Note that the AD9152-FMC-EBZ only uses the first 4 lanes, whereas all other
boards use 8 lanes.

This project assumes that the transceiver reference clock and SYSREF are
provided via the clock distribution chip that is found on the
ADxxxx-FMC-EBZ board.

In terms of pin connections between the FPGA and the FMC board the
AD9172-FMC-EBZ is very similar to the AD9144-FMC-EBZ.

The main differences are:
  * The DAC txen signals are connected to different pins
  * The polarity of the spi_en signal is active low instead of active high
  * The maximum lane rate is up to 15.4 Gpbs

To accommodate this 5 txctrl signals as well as the spi_en signal are connected
to GPIOs. Software can decide how to use them depending on which FMC board
is connected.

Note that each carrier has a maximum supported lane rate. Modes of the
AD9172 (and similar) that exceed the carrier specific limit can not be used
on that carrier. The limits are as following:
  * ZC706:  10.3125 Gbps
  * ZCU102: 15.4 Gbps (max AD9172 lanerate)

* SPI and GPIOs to PMOD header support

Connect a SPI interface and some GPIOs to the PL PMOD headers on the zcu102
and zc706 carriers.

This is can be used to control additional external hardware like a clock
chip or an analog front-end.

This is especially useful on FMC boards that do not feature a clock
generator chip.

The pin out is:
	PMOD  1: SPI clock
	PMOD  2: SPI chipselect
	PMOD  3: SPI MOSI
	PMOD  4: SPI MISO
	PMOD  7: GPIO 0
	PMOD  8: GPIO 1
	PMOD  9: GPIO 2
	PMOD 10: GPIO 3

The GPIOs are mapped at offset 48-51 of the EMIO GPIOs.
2019-06-06 11:45:05 +03:00
Laszlo Nagy 90f9b2c36a avl_dacfifo: add missing constraint 2019-06-06 11:45:05 +03:00
Istvan Csomortani 9afc871b70 a10gx: Optimise the base design
Add a clock crossing bridge for the interfaces that runs on a different
clock than the emif_user_clk.

This way we can simplify the main interconnect, and prevent occasional
timing violations.
2019-06-04 11:28:37 +03:00
Istvan Csomortani a7e3fcf26a adi_project_alt.tcl: Add comments to all proc 2019-05-31 10:32:40 +03:00
Istvan Csomortani 41bc947ac1 adi_project.tcl: Add comments to all proc 2019-05-31 10:32:40 +03:00
Istvan Csomortani 21031261b0 adi_board.tcl: Add comments to all proc 2019-05-31 10:32:40 +03:00
Istvan Csomortani 4d966500a8 adi_ip_alt.tcl: Add comments to all proc 2019-05-31 10:32:40 +03:00
Istvan Csomortani f2b3b7f493 adi_ip_alt.tcl: Delete deprecated procs 2019-05-31 10:32:40 +03:00
Istvan Csomortani 17afb4d9c5 adi_ip.tcl: Fix adi_add_multi_bus proc
The loop should iterate through the number of interfaces defined by the
$num attribute,
2019-05-31 10:32:40 +03:00
Istvan Csomortani bd43b565ce adi_ip.tcl: Add comments to all proc
Add doxygen support for all proc. Description of the used layout can be
find at http://www.doxygen.nl/manual/docblocks.html#tclblocks
2019-05-31 10:32:40 +03:00
Laszlo Nagy 08d01789c8 microblaze: add SPI clock constraint
The SPI clock is a generated clock from the system clock. Worst case
scenario is that the system clock is divided by two.
2019-05-30 14:55:11 +03:00
Laszlo Nagy 5986e87a1f zynq/zynqmp: create a 50MHz clock on the SPI clock outputs of the PS 2019-05-30 14:55:11 +03:00
Laszlo Nagy 70d7840c2b axi_fmcadc5_sync: define spi clock constraint
Create the spi clock based on input clock for the worst case scenario.
2019-05-30 14:55:11 +03:00
Laszlo Nagy 8390bf0ac6 adrv9361z7035:ccfmc_constr.xdc: constrain all input clocks 2019-05-30 14:55:11 +03:00
Laszlo Nagy aa0ea252ec fmcomms5: constrain ref clock 2019-05-30 14:55:11 +03:00
Laszlo Nagy 4fca24d41f vc707: define 125 MHz SGMII clock
Constrain the clock path to 125 MHz corresponding to the output of
ICS844021I which has a 25 MHz reference.
2019-05-30 14:55:11 +03:00