Commit Graph

5 Commits (e754f0a46a94a7ce9d139fbb0140ecb1094e4ee9)

Author SHA1 Message Date
Istvan Csomortani b9a5bb3549 axi_dacfifo: Optimize the AXI read logic
Save the valid AXI beats number of the last AXI transaction, and the valid
DMA beats number of the last AXI beat, so the read back logic can use this
data and prevent to feel up the CDC memory with invalid samples. Also in
this way the end of the read back cycle get a more robust control: no more
duplicated samples at the end of the buffer.
2016-07-20 11:49:06 +03:00
Istvan Csomortani e46990e508 axi_dacfifo: Cosmetic changes
Rename a few registers and fix indentation.
2016-07-20 11:49:06 +03:00
Istvan Csomortani e1495b89f9 axi_dacfifo: Cosmetic changes 2016-05-27 14:13:55 +03:00
Istvan Csomortani c8d4f956e7 axi_dacfifo: Update the read back logic
Update the readback logic of the FIFO. The controller uses a
relative address counter, which counts the DMA beats. The readback
logic uses the last value of that counter to define the wrapping
address. The aditional data from the last AXI burst, if there is any,
will be dropped.
2016-05-27 14:13:55 +03:00
Istvan Csomortani e855ef38f4 axi_dacfifo: Initial commit
AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.
2016-04-19 11:28:33 +03:00