Commit Graph

12 Commits (e6ac64c532718608efad130f0049a9e437af9dc8)

Author SHA1 Message Date
Bogdan Luncan 72313df81f Updated the makefiles to build the projects in subdirectories based on the build parameters.
Running 'make' will build the default project directly in the project folder (like it did before)
Running 'make RX_LANE_RATE=15 TX_LANE_RATE=15' will build the project inside the 'RXRATE15_TXRATE15' subdirectory.
Running 'make CFG=cfg/test_config.txt" will use the variables found inside the configuration file and build the project inside the 'test_config' subdirectory.
Running 'make clean' will clean the default project only.
Running 'make CFG=cfg/test_config.txt clean' will clean the 'testconfig' build.
Running 'make clean-all' will delete all the built configurations and libraries.

Note that the 'JESD' and 'LANE' words from the parameter names are stripped.

Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
2022-11-14 09:38:42 +02:00
LIacob106 158c10df34 projects: starndadize the jesd make parameters 2022-09-13 11:53:21 +03:00
Iacob_Liviu 482f0489a3 scripts: Merge adi_env.tcl into a single file
Move the new adi_env.tcl file from hdl/projects/scripts into hdl/scrips
2022-08-08 13:52:54 +03:00
Laszlo Nagy 8df1d8eade ad9081_fmca_ebz: Update parameter description 2022-03-11 13:16:22 +02:00
Laszlo Nagy 680d28476c ad9081_fmca_ebz: Add LANE_RATE param to all projects
The block design expects a lane rate to be set in the system project.
2021-05-14 15:39:40 +03:00
Laszlo Nagy bd6ec360e2 ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link
Set XCVR parameter for 204C 24.75 Gbps with a  dynamic range of 10Gbps..24.75Gpbs

Organize XCVR params based on lane rate
2021-05-14 15:39:40 +03:00
Laszlo Nagy 0374a7c1ac ad9081_fmca_ebz/vcu118: Added common 204C use cases as example 2021-02-05 15:24:15 +02:00
Laszlo Nagy d0f8a81b2f ad9081_fmca_ebz: Np 12 support
204B functional
204C functional
2021-02-05 15:24:15 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
Laszlo Nagy 7df4caf8b0 ad9081_fmca_ebz: Added parameter description
Add parameter description to project and common block design file
2020-04-23 17:21:05 +03:00
Laszlo Nagy e433d3f808 ad9081_fmca_ebz: expose PLL selection as a parameter
On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
  0 - CPLL
  1 - QPLL0
  2 - QPLL1

Since the selection of line rate is available from the project also the
PLL selection must be exposed.
2020-04-23 17:21:05 +03:00
Laszlo Nagy b1f62f09ac ad9081_fmca_ebz:vcu118: initial version
Use over-writable parameters from the environment.

      e.g.
        make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
        make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
        make JESD_MODE=8B10B  RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2020-03-10 18:19:03 +02:00