zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
6,132 Commits
1 Branch
0 Tags
23 MiB
Commit Graph

230 Commits (e4832cd027e0a27d6fdd31a2aab9780827b9b720)

Author SHA1 Message Date
Nick Pillitteri c1721e18dd account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores 2022-03-24 16:29:49 +02:00
Filip Gherman 9b7c2852b6 adxcvr: Increase version to 17.5.a 
Add suport for XCVR phase adjust buffer status:
   - Expose TXBUFSTATUS and RXBUFSTATUS
   - Create RXBUFSTATUS_RST flag for clearing RXBUFSTATUS
 2021-10-27 14:40:50 +03:00
LIacob106 076e81a17c library: Add link to wiki for IPs 2021-10-25 10:44:53 +03:00
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Filip Gherman 7ed4955661 axi_adxcvr_ip.tcl util_adxcvr_ip.tcl: Fixed asynchronous resets critical warnings in XCVR 2021-09-28 04:53:02 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Filip Gherman 0372ce1821 axi_adxcvr:util_adxcvr: Correctly defined resets. 2021-09-08 11:51:59 +03:00
stefan.raus 9d5de2fc21 Update Vivado version to 2020.2 
Update vivado version to 2020.2:
 - update default vivado version from 2020.1 to 2020.2
 - add conditions to apply specific contraints only in Out Of Context mode.
 - update DDR controler parameters for vcu118 and kcu105 dev boards
 2021-07-29 14:06:42 +03:00
Josh Blum e1829a061d adrv9001: fixes for reset metastability on xilinx ioserdes 
* fixes DRC warning that the clocking configuration may result in data errors
* fixes ioserdes reset issue with synchronous de-assert in data clock domain
 2021-07-09 11:11:04 +03:00
Laszlo Nagy 20161cf458 xilinx/axi_adxcvr/axi_adxcvr_mdrp: Fix read if all channels are selected 
If all channels are selected for read the values and ready signals from every
transceiver are combined. Each element merges his signals with the previous.
The first element of the chain must assume the previous channel is always ready.
 2021-06-25 14:15:59 +03:00
Laszlo Nagy 2995f78751 Revert "modified transceiver configuration files" 
This reverts commit 829e4155ca.

The first element of the read chain must assume there is no valid element
in front of it.  For each element the ready signal of the transceiver should be
routed if the channel is selected either by channel number or broadcast.
When the current element is not selected it should forward the ready signal from
the previous element, however this is not the case for the first one.

Having a constant 1'b1 connected to the ready input of the first element
corrupts the first read of the first channel after a channel switch.

This change will break broadcast reads.
 2021-06-25 14:15:59 +03:00
Laszlo Nagy bf77271fb3 axi_adxcvr: Increase version to 17.4.a 
Add support for:
  - 204C support for GTH
  - added second clock output for util_xcvr used in case for GTH
  - PROG_DIV support for GTH and GTY
 2021-06-10 09:53:43 +03:00
Laszlo Nagy 505142f7f8 xilinx/axi_adxcvr: Expose PLL status in status bit 2021-06-10 09:53:43 +03:00
Laszlo Nagy b4c8a559fc util_adxcvr: Hook up RXPROGDIVRESET 2021-06-10 09:53:43 +03:00
Laszlo Nagy d743406ecd util_adxcvr: Add 204C support for GTH3/4 
For GTH3/4  64b66b mode add a second clock that drives CLKUSR with a clock
that is 2x of the CLKUSR2 (lane rate/66),
   CLKUSR = 2 x CLKUSR2
   CLKUSR = lane rate / 33

This can be driven from the GT reference clock or second out clock div2.

This commit also:
- fix eyescan scale on GTY
- remove irrelevant parameters
 2021-06-10 09:53:43 +03:00
Laszlo Nagy c0775adac3 util_adxcvr/util_adxcvr_xch: Place 204C logic to a common place 2021-06-10 09:53:43 +03:00
Laszlo Nagy 9b50e2baa5 util_adxcvr/util_adxcvr_xch: Fix typo 2021-05-14 15:39:40 +03:00
Laszlo Nagy e1b73545e4 util_adxcvr: GTY TX phase and delay alignment circuit power down. 
Tied High when a) TX buffer bypass is not in use;
see UG578
 2021-05-14 15:39:40 +03:00
Laszlo Nagy ef69fe36db util_adxcvr: Add PPF1_CFG parameter 2021-05-14 15:39:40 +03:00
Laszlo Nagy 001e7a52b1 util_adxcvr: Add LANE_RATE parameter so it can be used for automatic constraint generation 
Add separate LANE_RATE for TX and RX
 2021-05-14 15:39:40 +03:00
Laszlo Nagy cb5e66ff9c xilinx/util_adxcvr: 204C link support for GTY4 
Set channel parameters based on link mode (1 - 204b or 2 - 204c).
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 2d13b5b8cd xilinx/axi_adxcvr: Add 204C support, increase version to 17.3.a 2021-05-14 15:39:40 +03:00
Laszlo Nagy cdd6c92357 xilinx/axi_adxcvr: Increase version to 17.02.a to show PRBS capability 2021-03-22 10:17:10 +02:00
Laszlo Nagy 5f2681314f xilinx/axi_adxcvr/axi_adxcvr_up: Fix force error control bit 2021-03-22 10:17:10 +02:00
Laszlo Nagy 6f4053f3b0 util_adxcvr: Fix PRBS synchroniser typo 
The control lines for TX PRBS must be synchronized using the TX clock.
 2021-01-29 14:01:25 +02:00
Laszlo Nagy 14307856ea xilinx:adxcvr: PRBS support 
The new REG_PRBS_CNTRL and REG_PRBS_STATUS registers expose controls of internal
PRBS generators and checkers allowing the testing the multi-gigabit serial link
at the physical layer without the need of the link layer bringup.
 2021-01-12 13:40:42 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific 
Updated all system_project and Makefiles
 2020-11-02 16:13:35 +02:00
Laszlo Nagy 4e438261aa ad_serdes_out: Add CMOS support 2020-08-07 08:31:19 +03:00
Laszlo Nagy 837475db0d ad_serdes_in: Add CMOS support 2020-08-07 08:31:19 +03:00
Laszlo Nagy e6b9e21ad1 ad_serdes_out: Add tristate option 2020-08-07 08:31:19 +03:00
Laszlo Nagy c5c772127d up_delay_cntrl:ad_serdes_in: Make delay value width parametrizable 
US/US+ devices have IDELAY/ODELAY with 512 taps. This requires wider
control value for delay selection. 9 bits contrary to 5 on 7series.
 2020-08-07 08:31:19 +03:00
Laszlo Nagy 37d378c753 common/ad_serdes_out.v: Add US/US+ support 2020-08-07 08:31:19 +03:00
Laszlo Nagy 65d39b9164 common/ad_serdes_in.v: Add US/US+ support 2020-08-07 08:31:19 +03:00
Laszlo Nagy cf145ca961 axi_adxcvr: Reset status if PLL lock is lost 
In case something happens with the reference clock of the CPLL or QPLL,
they might lose the locking. The status should reflect that.
 2020-07-31 11:43:41 +03:00
Istvan Csomortani 32eeedb660 makefile: Update makefiles 2020-05-07 08:41:49 +01:00
Laszlo Nagy 8af5f65ff2 util_adxcvr: enable EyeScan for GTY4 2020-03-10 18:17:38 +02:00
Adrian Costina 0d4aa7c01e axi_dacfifo: Allow datawidths larger than the AXI datawidth 2020-02-18 11:19:02 +02:00
Laszlo Nagy ea06fcd7b6 util_adxcvr: add GTY4 parameters for 15.5Gbps lanerate 2020-02-10 09:48:17 +02:00
Laszlo Nagy 253b1149ad library/xilinx/util_adxcvr: merge GTY and GTH prefixed parameter 
parameters with same names were duplicated with transceiver specific
names due different default values.
This does not scales very well.

Use same name for the parameters as for other parameters and do the
default value handling in the IP configuration layer.
 2020-02-10 09:48:17 +02:00
Arpadi 80a77b1e1b ad_rst_constr: Added the quiet option 
critical warnings were caused by this file when the ad_rst.v instantiation
was done using generate depending on a parameter (i.e. axi_spi_engine)
 2020-01-20 15:26:48 +02:00
Arpadi 53cb087b9c ad_rst_constr: changed hier to hierarchical 2020-01-13 12:25:23 +02:00
Istvan Csomortani d2d7f2a3f9 up_clk_mon_constr: -heir is deprecated, use hierarchical instead 2020-01-13 12:25:23 +02:00
Istvan Csomortani 87a752e242 ad_rst_constr: Search pin in all hierarchy 2020-01-13 12:25:23 +02:00
Arpadi 3235c9189c axi_xcvrlb: added new parameters to IP 
added PLL locked reg to axi regmap; IP now recognizez xcvr type
automatically
 2020-01-07 16:18:33 +02:00
Adrian Costina 39d19ef401 util_adxcvr: Add additional parameters allowing for GTH4 RX 15Gbps rates 2019-11-11 14:46:09 +02:00
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
Adrian Costina f2d2092297 axi_dacfifo: Add don't touch for the constraints to apply 2019-08-01 18:15:45 +03:00
Arpadi fe09acaa2f up_axi_update: ADDRESS_WIDTH parameter is now a localparam 
ADDRESS_WIDTH is now AXI_ADDRESS_WIDTH - 2;
up_axi instantiations will set AXI_ADDRESS_WIDTH instead of ADDRESS_WIDTH;
 2019-07-26 11:58:58 +03:00
Istvan Csomortani 04ce10a570 cosmetics: Change Altera to Intel in comments 2019-06-29 06:53:51 +03:00
Istvan Csomortani b0fbe1bb57 util_clkdiv: Seperate the IP source into an intel and xilinx version 2019-06-29 06:53:51 +03:00