e4832cd027
ad9208_dual_ebz: Update Board Product Page link
2022-03-25 10:42:40 +02:00
c1721e18dd
account for ADI_VIVADO_IP_LIBRARY global variable when adding subcores
2022-03-24 16:29:49 +02:00
0d9e9e42c0
sidekiqz2: Updated Readme to link the ADALM-Pluto documentation
2022-03-24 16:29:11 +02:00
aa1192a9bc
ad_quadmxfe1_ebz_bd: Connecting all the unused lanes in util_xcvr
2022-03-23 08:13:09 +02:00
101874de86
projects/scripts/adi_board.tcl: Fix padding error caused by lane_map in ad_xcvrcon procedure
2022-03-23 08:12:49 +02:00
6a252ec067
util_mii_to_rmii: Fix 100 Mbps configuration functionality
2022-03-22 14:30:24 +02:00
4499ddaae7
pluto_ng: Add Readme.md file
2022-03-22 11:43:44 +02:00
e22a597752
adrv2crr_fmcxmwbr1: Initial commit
2022-03-18 10:19:40 +02:00
084d44c978
add ability to customize Xilinx IP library version to value other than "user" from a global variable.
2022-03-17 09:43:39 +02:00
0f8cc9e66b
ad9083: Using variables instead of hard coded nets
2022-03-15 10:53:31 +02:00
8df1d8eade
ad9081_fmca_ebz: Update parameter description
2022-03-11 13:16:22 +02:00
5ced589258
ad9082_fmca_ebz: Update parameter description
2022-03-11 13:16:22 +02:00
081de06ec9
ad_quadmxfe1_ebz: Update parameter description
2022-03-11 13:16:22 +02:00
e66c5282bc
axi_adrv9001: Expose IODELAY_CTRL parameter to top level
2022-03-02 11:06:12 +02:00
a21cd9932d
adrv9001_zed: Fix irq overlap
...
axi_adrv9001_tx1_dma/irq is no longer dissconnecting axi_iic_fmc/irq
2022-03-01 16:42:52 +02:00
d4fb7062d9
vcu128/vcu128_system_constr: Enable internal diff term for Ethernet clock
...
There are no external termination resistors on the VCU118 and VCU128 for
the SGMII clock lines.
The board files of the VCU118 enables them, but this was not reflected in the
constraint files.
For VCU128 the clocking is similar, even if diff terms are not set in the
board files we should have a consistent approach with the VCU118.
2022-02-16 14:09:20 +02:00
c871a3a9ee
vcu118/vcu118_system_constr: Enable internal diff term for Ethernet clock
...
There are no external termination resistors on the VCU118 for the SGMII
clock lines. The board files enables them, but this was not reflected in the
constraint files.
2022-02-16 14:09:20 +02:00
4c7be950d1
ad_ip_jesd204_tpl_adc: Fix latency of valid signal
2022-02-16 10:27:50 +02:00
5edf6c19de
adrv9009/zcu102: Hook up ref clock from IBUFDS_GT
2022-02-15 11:09:37 +02:00
4bd55dc5c2
adrv9009/zc706: Hook up ref clock from IBUFDS_GT
2022-02-15 11:09:37 +02:00
aac4746398
adrv9009/common/adrv9009_bd: Take ref clock from the IBUFDS_GT
...
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset or misconfigured. This will stop the clock generators from getting
a clock prior removing the reset of the XCVR. The XCVR has a requirement
of running user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
2022-02-15 11:09:37 +02:00
3c6c45962a
adrv9371x/kcu105: Hook up un-gated ref clock to fabric
2022-02-15 11:09:37 +02:00
572005abe4
adrv9371x/zcu102: Hook up un-gated ref clock to fabric
2022-02-15 11:09:37 +02:00
501903bc81
adrv9371x/zc706: Hook up un-gated ref clock to fabric
2022-02-15 11:09:37 +02:00
39e073e6bf
adrv9371x: Use the output of IBUFDS_GTE2 as reference for the clock gens
...
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset. This will stop the clock generators from getting a clock prior
removing the reset of the XCVR. The XCVR has a requirement of running
user clock while removing the reset. The correct sequence must be :
Enable device clocks (user clock)
Remove the reset from the XCVR
2022-02-15 11:09:37 +02:00
86d754ae85
projects/scripts: Add gtwizard scripts
2022-02-14 10:32:58 +02:00
62dc310794
Revert "intel: Update projects to use ad_iobuf instead of ALT_IOBUF"
...
This reverts commit a3a610728c
2022-02-09 17:39:29 +02:00
4790d334ad
dac_fmc_ebz: NUM_LINKS added to system_top.v
2022-02-09 12:23:12 +02:00
7702079af5
ad_quadmxfe1_ebz: Fix external sync for ADC path
2022-02-08 16:56:01 +02:00
3ff2887485
dac_fmc_ebz_vcu118: Initial commit
2022-02-08 14:34:47 +02:00
694ebbfbfc
dac_fmc_ebz_bd.tcl: Updated bd for multiple tx_ref_clk
2022-02-08 14:34:17 +02:00
45dae0f3d3
ad9081_fmca_ebz/common: Connect sync at TPL level
...
Reset CPACK from ADC TPL so during armed capture clear the cpack to avoid
capturing old samples.
Reset UNPACK with TPL to clear upack during armed transfers to avoid
sending old data.
2022-02-07 19:14:01 +02:00
8ec657315c
adrv9009zu11eg: Drive cpack/upack reset from TPL
2022-02-07 19:14:01 +02:00
d949936a1b
adrv9009zu11eg/common: EXT_SYNC updates
...
- Explicitly enable EXT_SYNC parameter for Rx/Obs
- Loopback manual sync for each TPL (we do not combine them yet because
it requires extra CDC logic)
2022-02-07 19:14:01 +02:00
f245448976
ad_ip_jesd204_tpl_ : Add missing dependency
2022-02-07 19:14:01 +02:00
b5092662d5
ad_ip_jesd204_tpl_adc: Refactor external sync
...
- Add EXT_SYNC option
- Gate valid while in reset
2022-02-07 19:14:01 +02:00
8c7cca4277
common/up_adc_common: Add ext sync regs
2022-02-07 19:14:01 +02:00
1b06c74919
common/up_dac_common: Add manual sync request
2022-02-07 19:14:01 +02:00
db49aa652f
common/up_dac_common: Add support for explicit disarm control
2022-02-07 19:14:01 +02:00
4e644e4e74
jesd204/ad_ip_jesd204_tpl_dac: External sync refactor
...
- Expose EXT_SYNC parameter to sw
- Add external manual sync request
- Add rst to interface
2022-02-07 19:14:01 +02:00
1ca5abc91e
common/up_xfer_cntrl: Fix transfer done timing
...
up_xfer_done should signalize when a previous control set is
transferred to the other clock domain and the current control set is latched.
If a bit from the up_data_cntrl changes, it should stay in that state until
the up_xfer_done asserts.
2022-02-07 19:14:01 +02:00
63a1233101
ad7134_fmc: Update Readme
2022-02-07 14:41:25 +02:00
4827e5eb18
ad7134_fmc: Switch offload trigger to falling ODR
2022-02-07 14:41:25 +02:00
297bed6721
ad7134_fmc: Change ODR signal to output
...
FPGA is now generating the ODR signal using axi_pwm_gen.
Both ADCs are now in slave mode.
2022-02-07 14:41:25 +02:00
b63ebca292
projects/cn0506_rmii/*: Add util_mii_to_rmii library to project
2022-02-03 10:23:12 +02:00
170ce42e3e
util_mii_to_rmii: Initial commit
2022-02-03 10:23:12 +02:00
3da9d9fcb4
pluto_ng: Initial commit
2022-02-03 09:56:13 +02:00
7dae0858b0
de10nano: changed quartus version to 20.1.1
2022-01-31 14:10:51 +02:00
38f3627695
ad_dds: Fix DDS start samples
...
When using a CLK_RATIO > 1 the first n samples(n=CLK_RATIO) after sync, are
noisy. This is because the phase accumulator data is passed to the phase to
amplitude converter, during the phase synchronization step.
2022-01-31 14:07:11 +02:00
bc5974d789
ad77681evb: Fix irq overlap
...
spi engine irq signal was overwriting fmc iic irq
2022-01-31 12:32:31 +02:00
Adrian Costina
Nick Pillitteri
Filip Gherman
alin724
AndreiGrozav
Stanca Pop
Ionut Podgoreanu
Laszlo Nagy
sergiu arpadi
LIacob106
alin724