e2ef470150
axi_ad9434: Fix input data rate
2017-05-04 16:38:21 +03:00
db459d96e9
daq2: zc706: Increase DAC FIFO size
...
Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is
quite a limiting size for practical applications. Increase the size to 1MB
to allow loading larger waveforms.
In this configuration the DAC FIFO will use half of the available BRAM
cells in the FPGA. This still leaves quite a few BRAMs available for
user application logic added to the design. If a user design should run out
of BRAMs nevertheless they can reduce the FIFO size, if not required by the
application, to free up some cells.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-28 11:34:45 +02:00
edefb9df44
axi_hdmi_tx: Fix assignment type
...
The general rule of thumb is to use nonblocking assignments for
sequential always blocks.
2017-04-21 09:06:54 +03:00
54ff4d7bd0
ad_serdes_in: Fix generate block
2017-04-20 19:47:45 +03:00
7659700719
ad_serdes_clk: Fix generate block
2017-04-20 19:47:19 +03:00
03dcbc6a7d
ad_mmcm_drp: Fix generate block
...
Can not be multiple 'if' statements inside a generate block. If there are
multiple cases use if/esle statement, but always should be one single
if/else inside a generate.
2017-04-20 19:43:46 +03:00
01165c926c
ad6676evb: Set default xcvr parameters to common design
2017-04-18 11:26:51 +03:00
ee398b4703
spi_engine: Fix CMD_FIFO_VALID generation
...
Because of the memory map interface mux, up_waddr_s and up_wreq_s should be
used, when cmd_fifo_in_valid is generated.
2017-04-12 14:43:00 +02:00
7c191a089f
fmcjesdadc1: Update xcvr configuration to the default one used for this board
2017-04-12 14:41:43 +03:00
75409eeb38
util_fir_int: Shifted data so that the amplitude at the output of the filter is the same with the input
2017-04-12 13:49:53 +03:00
096aadbf91
util_fir_dec: Changed output rounding mode to Symmetric rounding to Zero
...
This removes the added DC component that was introduced by the previous rounding mode
2017-04-12 13:49:37 +03:00
f7190dbbfd
adxcvr: Update Makefiles
2017-04-03 12:38:40 +03:00
fa5f81f6c6
axi_dacfifo: Fix clock for read address generation
2017-04-03 10:39:17 +03:00
7cb7bc111e
axi_dacfifo: Delete unused wires
2017-04-03 10:38:50 +03:00
14b4c4cf5f
axi_dacfifo: Define constraint for bypass
...
The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-04-03 10:38:28 +03:00
06605ed1e1
axi_dacfifo: Register the dac_valid signals
2017-04-03 10:38:09 +03:00
77081a6233
axi_dacfifo: Data from DMA is validated with dma_ready too
2017-04-03 10:37:45 +03:00
af3a4f5fc9
axi_dacfifo: axi_dvalid should come from dacfifo_rd module
2017-04-03 10:37:30 +03:00
b30041f7f3
axi_dacfifo: Redesign the bypass functionality
2017-04-03 10:37:08 +03:00
434d1ea52c
axi_dacfifo: Fix constraints
2017-04-03 10:36:46 +03:00
4bda798f13
Merge branch 'dev' into hdl_2016_r2
...
Update the release branch with all the recent fixes.
2017-02-21 10:56:52 +02:00
040b61de60
fmcadc5: Updated default parameters
2017-02-20 17:13:58 +02:00
a15e05c497
adcfifo- remove axi-byte-width parameter
2017-02-17 15:29:10 -05:00
cb3d1883bc
fmcjesdadc1/a5gt- hard placement of ddr hr/qr registers
2017-02-17 15:21:33 -05:00
981a61bf16
axi_dacfifo: Clean up the axi_dacfifo_wr.v module
2017-02-17 18:40:02 +02:00
3e5054247b
scripts: For altera projects, when it doesn't meet timing rename the generated sof
2017-02-17 11:08:50 +02:00
e8bcbb74da
scripts: fixed tcl syntax for altera projects not meeting timing
2017-02-16 21:21:51 +02:00
f10866e4c3
axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter
2017-02-16 19:54:41 +02:00
95a4ea20c8
axi_dacfifo: Delete redundant parameter BYPASS_EN
2017-02-16 19:53:44 +02:00
8453d758c2
scripts: If an altera project doesn't meet timing, rename the sof
2017-02-16 19:20:49 +02:00
343d0472d4
fmcadc2: Move GT setting to common/system_bd.tcl
2017-02-16 14:56:25 +02:00
07184b31d2
fmcadc2: Define default clock selection for Xilinx GTs
2017-02-16 12:35:24 +02:00
358aa48c76
axi_adc_decimate: Fix assignment width
2017-02-15 11:38:43 +02:00
86c279c238
pzsdr1: ccbox, moved I2S core to DMA0 and DMA1 to fix critical warnings
2017-02-14 14:51:49 +02:00
46290193f3
pzsdr2: ccusb, renamed clk_out to clkout_in
2017-02-14 11:58:11 +02:00
27119343f2
pzsdr2: ccusb, connect unused clock pins to GND
2017-02-14 11:56:54 +02:00
fa37f4dd0a
pzsdr2: Don't set a disabled parameter
2017-02-14 11:56:08 +02:00
6a9b7580de
pzsdr1: ccusb, renamed clk_out to clkout_in
2017-02-14 11:54:46 +02:00
acef0113d1
pzsdr1: ccusb, connect unused clock pins to GND
2017-02-14 11:50:37 +02:00
46883731eb
pzsdr1: Don't set a disabled parameter
2017-02-14 11:50:06 +02:00
c6ee76421b
axi_usb_fx3: Fixed clock domain association
2017-02-14 11:48:07 +02:00
a569b6bf0c
pluto: Interpolation, connect fifo_rd_valid to s_axis_data_tvalid
2017-02-13 18:08:52 +02:00
7c86b038ef
util_fir_int: manually request data at 1/8 clock frequency
2017-02-13 18:05:59 +02:00
e215a091b2
m2k: standalone, added explicit fclk_clk0 and fclk_clk1 constraints
2017-02-13 12:02:59 +02:00
4e62fb0ef3
m2k: Add reset circuitry on the logic_analyzer clock domain
2017-02-13 12:02:11 +02:00
5fa6dba333
Make: Update Makefiles
2017-02-10 16:32:58 +02:00
f5f1f47691
ad9467_fmc: Delete asynchronous clock group definition
...
This is a very bad way to handle timing. All the false path
should be defined explicitly, rather than define asynchronous clock
domains.
2017-02-10 16:21:35 +02:00
0dae754f2d
axi_adxcvr: Add rparam register to Altera XCVR
2017-02-10 16:19:17 +02:00
24daffcf5c
spi_engine: Set up default driver value for input ports
2017-02-07 12:30:46 +02:00
47db0d80fe
axi_ad7616: Set up default driver value for input ports
2017-02-07 12:29:21 +02:00
AndreiGrozav
Lars-Peter Clausen
Istvan Csomortani
Adrian Costina
Rejeesh Kutty