When channels are not swapped in groups of four but are completely out of order
the common control channel can't be reordered based on the index of the
channel.
The DDR controller for C2 for is much closer to the transceivers which
connect to the FMCp connector so designs does not have to span over all
three SLRs just over two reducing implementation and timing closure effort.
The second ADC was removed from the project, as the EV-AD7768-1FMCZ evaluation
board contains only one ADC. Therefore, all the IPs related to the
second ADC have been removed, too.
The data width supported by the spi IPs has been changed from 8 bits to
32 bits, therefore the axis_upscaler(util_axis_upscale_v1_0) and the
m_axis_samples_24(AXI4-Stream Data Width Converter) are no more necessary,
so they have been removed from the design.
The 24 bits width data transfer between the s_axis of axi_ad77681_dma
(AXI DMA Controller) and the offload_sdi of the spi_engine_offload is now made
directly.
Add commands to generate one extra file with resource utilization, in CSV format.
New commands executes only if ADI_GENERATE_UTILIZATION env variable is set.
In ZCU102 LA01_CC_P|N are connected to regional clock, but in order to
receive a device clock properly we have to use pin which is connected
to a global clock buffer. Luckily SYSREF is connected to global clock
pin; swap to port to receive the device clock correctly.
Also, swap the ports in both ZC706 and A10SOC carriers.
mclk now generated by ps not axi clkgen ip. ADAU1761 expects a free
running clock and the i2s driver was switching the axi clkgen ip off
which was causing issues.
Cleanup placement constraints and let the tool have more freedom to
place and route the design. This is possible only after balancing the
memory and system clocks.
Minimize skew on synchronous CDC timing paths between clocks originating
from the same MMCM source. (sys_mem_clk and sys_cpu_clk)
This is required mostly by the smart interconnect.
The CLOCK_DELAY_GROUP property must be applied directly to the output net of BUFGs.
"prepare_incremental_compile" is defined as a phony target, but is also a
prerequisite of a real target. This will lead to a complete project build
every time make is called.
To fix the issue the functionality of prepare_incremental_compile target
was included in the generic project build target.
Software has to know which TIA channel was used for a particular capture.
Define an additional dummy ADC channel which will provide this
information. Currently this channel is always enabled.
This commit was created by squashing the following commits, these
messages were kept just for sake of history:
ad9694_500ebz: Mirror the SPI interface to FMCB
ad9694_500ebz: Set transceiver reference clock to 250
ad9694_500ebz: Allow to configure number of lanes, number of converters
and sample rate
axi_ad9694: Fix number of lanes, it must be 2
ad9694_500ebz: Update the mirrored spi pin assignments
ad9694_500ebz: Gate SPI MISO signals based on chip-select
ad9694_500ebz: Set channel pack sample width
ad9694_500ebz: Change reference clock location
ad9694_500ebz: Remove transceiver memory map arbitration
ad9694_500ebz: Ensure ADC FIFO DMA_DATA_WIDTH is not larger ADC_DATA_WIDTH
ad9694_500ebz: Adjust breakout board pin locations
ad_fmclidar1_ebz: Rename the ad9694_500ebz project
ad_fmclidar1_ebz: Fix lane mapping
ad_fmclidar1_ebz: Delete deprecated files
ad_fmclidar1_ebz: Integrate the axi_laser_driver into the design
ad_fmclidar1_ebz: OTW is an active low signal
ad_fmclidar1_ebz: zc706: Fix iic_dac signals assignment
ad_fmclidar1_ebz: Switch to util_adcfifo
ad_fmclidar1_ebz: Enable synced capture for the fifo
ad_fmclidar1_ebz/zc706: Enable CAPTURE_TILL_FULL
ad_fmclidar1_ebz/zc706: Reduce FIFO size to 2kB
ad_fmclidar1_ebz: Laser driver runs on ADC's core clock
ad_fmclidar1_ebz_bd: Delete the FIFO instance
Because the DMA transfers are going to be relatively small (< 2kbyte),
the DMA can handle the data rate, even when the frequency of the laser
driver pulse is set to its maximum value. (200 kHz)
The synchronization will be done by connecting the generated pulse to
the DMA's SYNC input. Although, to support 2 or 1 channel scenarios, we
need to use the util_axis_syncgen module to make sure that the DMA
catches the pulse, in cases when the pulse width is too narrow. (SYNC is
captures when valid and ready is asserted)
Also we have to reset the cpack IP before each pulse, to keep the DMA buffer's
relative starting point in time fixed, when only 2 or 1 channel is
active.
Our internal repository was changed from phdl to ghdl. Update the
adi_env.tcl scripts and other scripts, which depends on the $ad_ghdl_dir
variable. This way the tools will see all the internal IPs too.
István Csomortáni
Prasahnt Sivarajah
Adrian Costina
Istvan Csomortani
AndreiGrozav
Laszlo Nagy
Stanca Pop
Sergiu Arpadi
Stefan Raus
StancaPop