Commit Graph

8 Commits (e112a03d8596e5aba78253e93177d0cb5bd275f6)

Author SHA1 Message Date
Laszlo Nagy ef15757d9e common:vcu118: support for plddr4 adc and dac fifo
Use 1GB from the DDR4 for either ADC or DAC sample buffering.
Max theoretical bandwidth of 19.2 GB/s
2020-03-03 15:49:11 +02:00
Laszlo Nagy c2726ceac9 common:vcu118: move system memory to DDR C2
The DDR controller for C2 for is much closer to the transceivers which
connect to the FMCp connector so designs does not have to span over all
three SLRs just over two reducing implementation and timing closure effort.
2019-11-28 16:17:44 +02:00
Laszlo Nagy b7d48b8c74 common/vcu118: Balance clocks
Minimize skew on synchronous CDC timing paths between clocks originating
from the same MMCM source. (sys_mem_clk and sys_cpu_clk)
This is required mostly by the smart interconnect.
The CLOCK_DELAY_GROUP property must be applied directly to the output net of BUFGs.
2019-09-16 10:00:14 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Istvan Csomortani de510b45ab base: Add system_processor_rst for all the global clocks 2019-06-11 18:13:06 +03:00
Istvan Csomortani 20c714eccf common: Define three global clock nets
For all the Xilinx base design, define three global clock nets, which
are saved in the following three global variable: $sys_cpu_clk, $sys_dma_clk
and $sys_iodelay_clk.

These clock nets are connected to different clock sources depending of
the FPGA architecture used on the carrier. In general the following
frequencies are used:

  - sys_cpu_clk     - 100MHz
  - sys_dma_clk     - 200MHz or 250Mhz
  - sys_iodelay_clk - 200MHz or 500Mhz
2019-06-11 18:13:06 +03:00
Laszlo Nagy 08d01789c8 microblaze: add SPI clock constraint
The SPI clock is a generated clock from the system clock. Worst case
scenario is that the system clock is divided by two.
2019-05-30 14:55:11 +03:00
Adrian Costina dc5f90098e vcu118: Initial commit for common files 2019-04-17 14:24:35 +03:00