Commit Graph

19 Commits (e112a03d8596e5aba78253e93177d0cb5bd275f6)

Author SHA1 Message Date
AndreiGrozav 78afe38a3f adrv9009: Add decimation and interpolation filters 2019-08-20 16:24:47 +03:00
AndreiGrozav 36a1767329 Add generic fir filters processes for RF projects 2019-08-20 16:24:47 +03:00
Istvan Csomortani 424abe0c02 adrv9009: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 0e750bea42 adrv9009: Fix dma_clk tree 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables
Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
Istvan Csomortani 391ac468a7 adrv9009/common: Fix ad_xcvrcon proc call
The process ad_xcvrcon has a device_clk attribute which can be used to
connect a custom device clock to the XCVR. Fix the proc call so we can
simplify the block design script.
2019-05-29 10:27:16 +03:00
Laszlo Nagy c930395773 adrv9009:qsys: use bundled AXIS interface 2019-05-16 13:27:19 +03:00
Laszlo Nagy 3183fbf226 adrv9009: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy c9f1c92eaa adrv9009: use generic TPL
Make the block design parametrizable.
Limitations:
  F = 1,2,4
2018-12-21 17:32:48 +02:00
Adrian Costina e09f3290ff adrv9009: Move intel project to upack2/cpack2 2018-12-03 12:23:24 +00:00
Lars-Peter Clausen 2462f8e50f adrv9009: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Adrian Costina e4048c7b04 adrv9009: A10SOC: Add second observation channel 2018-11-27 15:31:21 +02:00
Adrian Costina f12bd3d246 adrv9009: A10SOC: Initial commit 2018-11-27 15:31:21 +02:00
Istvan Csomortani 1931d65b7a adrv9009/zcu102: Update initial configuration for GT clock output control 2018-10-04 14:37:02 +03:00
Adrian Costina 41e717ec2c adrv9009: Added option for enabling the second observation channel 2018-06-29 11:10:39 +03:00
Adrian Costina e982232d75 adrv9009: Increased DMA clock frequency to ~333 MHz, by enabling AXI SLICES for DMAs 2018-06-12 23:53:56 +03:00
Adrian Costina f3ac5d3ad3 adrv9009: Increase all DMAs MAX_BYTES_PER_BURST to 256 2018-06-12 23:53:56 +03:00
Adrian Costina e445fbe04f adrv9009: Improved data throughput and DAC FIFO size
Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA
HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time.
HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller
All HPx and DMA buswidths have been increased to 128 bits
The HPx-DMA clock has been increased to 300 MHz
DAC FIFO address size has been increased to 17
2018-05-14 11:33:04 +03:00
Adrian Costina e4d579726d Renamed ad9379 to adrv9009 2018-04-26 18:19:11 +03:00