Istvan Csomortani
64d1948ea0
axi_ad7616: Initial commit
2015-11-10 13:32:56 +02:00
Adrian Costina
5cc97c78d3
Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries
2015-11-10 09:32:50 +02:00
Istvan Csomortani
ef9bdf6ec9
adi_project: Regenerate the layout of the IP Integrator subsystem design.
2015-11-09 11:01:10 +02:00
Istvan Csomortani
214adbfd85
ad7616_sdz_zc706: Add board related IO's to system top.
2015-11-09 10:51:46 +02:00
Rejeesh Kutty
1d6254fdec
pzsdr/ccbrk: loopback board support
2015-11-06 11:34:21 -05:00
Adrian Costina
e7fd964874
axi_clkgen: Added a second input clock option
2015-11-06 17:55:29 +02:00
Adrian Costina
afc4274ee3
common scripts: Changed the resulting hdf file to system_top_bad_timing, if design doesn't meet timing.
2015-11-06 16:01:19 +02:00
Adrian Costina
0c7c0f2cd8
common scripts: Change the name of the generated HDF if the design doesn't meet timing
2015-11-05 18:41:51 +02:00
Rejeesh Kutty
11718291cf
pzsdr/ccfmc- add single loopback core
2015-11-05 11:28:38 -05:00
Rejeesh Kutty
839e76996f
axi_gpreg: added constraints
2015-11-05 11:28:37 -05:00
Rejeesh Kutty
482b740229
axi_gpreg: add buffer enable
2015-11-05 11:28:35 -05:00
Rejeesh Kutty
66d4f8fd58
util_gtlb: output receive/transmit clocks
2015-11-05 11:28:34 -05:00
Rejeesh Kutty
9e27a60478
pzsdr/ccfmc- single loopback core
2015-11-05 11:28:33 -05:00
Rejeesh Kutty
28bfeb442c
util_gtlb- syntax error fixes
2015-11-05 11:28:31 -05:00
Adrian Costina
e36f27b061
daq2: Update A10GX project, with the latest changes.
...
Works with up to 64k samples
2015-11-04 14:54:09 +02:00
Adrian Costina
83399ef6ee
a10gx: Updated common project to work with Linux (enabled MMU)
2015-11-04 13:35:52 +02:00
Adrian Costina
6d28a92b5b
util_adcfifo: Added altera initial constraints file
2015-11-04 13:34:52 +02:00
Adrian Costina
e8b84b3662
axi_dmac: Updated axis destination / source ports for altera component
2015-11-04 13:33:41 +02:00
Adrian Costina
de53a61902
util_adcfifo: Put a limit on the read/write address from memory so there is no overflow
...
Added altera component
2015-11-04 13:31:50 +02:00
Adrian Costina
6cfc13a9dd
common: Allow for the memory to be also symetrical
2015-11-04 13:28:02 +02:00
Rejeesh Kutty
ad1cef1441
axi_gpreg: compile fixes
2015-11-03 14:29:00 -05:00
Rejeesh Kutty
c8019b69fd
axi_gpreg- added
2015-11-03 14:28:59 -05:00
Rejeesh Kutty
88f247a1de
util_gtlb: use gpio
2015-11-03 14:28:57 -05:00
Istvan Csomortani
27266c59ee
ad7616_sdz: Add project source files
2015-11-03 15:03:35 +02:00
Istvan Csomortani
cf58110a98
Merge branch 'dev' into dev_ad7616
2015-11-03 14:07:48 +02:00
Lars-Peter Clausen
a0039ed4fe
ccfmc: Launch HDMI data on falling edge
...
The ADV7511 captures data on the rising edge, so make sure to launch data
on the falling edge. This fixes some issues with image stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
Lars-Peter Clausen
acd9efc528
axi_hdmi_tx: Add parameter to configure the output clock polarity
...
In order to maximize the window where it is safe to capture data we ideally
want to launch data on the opposite edge to which it is captured. Since the
edge on which data is captured depends on the connected device add a
parameter that allows to configure the launching edge.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
Rejeesh Kutty
6dddac5d94
ccfmc- missing board io
2015-11-02 15:45:14 -05:00
Rejeesh Kutty
cafc80c829
fmcadc5: add programmable io delay
2015-11-02 12:10:18 -05:00
Istvan Csomortani
a147acd791
spi_engine: Add support for multiple SDI lines.
...
By changing the parameter called SDI_DATA_WIDTH the spi framework can support multiple SDI lines.
The supported number of SDI lines are: 1, 2, 3 and 4.
2015-11-02 18:42:55 +02:00
Rejeesh Kutty
8b95520767
pzsdr/ccfmc- add loopback gpio/gt cores
2015-10-30 18:48:26 -04:00
Rejeesh Kutty
88568c21e1
util_gtlb: updates for latest axi_jesd_gt
2015-10-30 18:47:36 -04:00
Rejeesh Kutty
92b7570864
pzsdr/ccfmc- add ad9517 signals
2015-10-30 10:50:53 -04:00
Rejeesh Kutty
b3cb84cf91
fmcadc5- added ila
2015-10-29 16:48:21 -04:00
Rejeesh Kutty
24d76c610a
fmcadc5- fix core connections
2015-10-29 16:47:56 -04:00
Rejeesh Kutty
ac4091e19e
fmcadc4- add monitor fifo
2015-10-27 14:52:02 -04:00
Rejeesh Kutty
2b6ae00a44
library: add mfifo
2015-10-27 14:52:02 -04:00
Adrian Costina
b5d3d0bd13
usb_fx3: Added axi_usb_fx3 core and DMA to the project
2015-10-27 09:41:18 +02:00
Rejeesh Kutty
748a2bc87a
fmcadc4- add ila for zc706 only
2015-10-23 14:32:35 -04:00
Rejeesh Kutty
b2d0f5c56e
fmcadc4- use the same source/name for clocks
2015-10-23 14:32:35 -04:00
Rejeesh Kutty
f1ed27105f
library/common- reset fix
2015-10-23 14:32:35 -04:00
Adrian Costina
32b3cfd8b9
axi_usb_fx3: Initial commit of the core with interface stub
2015-10-23 13:27:00 +03:00
Adrian Costina
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
Rejeesh Kutty
cb2bda48c0
fmcadc5- gt/ip updates
2015-10-19 09:31:32 -04:00
Rejeesh Kutty
ed918ec119
imageon - keeping scripts happy
2015-10-16 15:04:02 -04:00
Rejeesh Kutty
e14e9294c5
project-names -- variables causes scripts to fail- too much parsing
2015-10-16 14:13:56 -04:00
Istvan Csomortani
36dd6427fe
pzsdr: Add untracked Makefiles
2015-10-16 13:58:36 +03:00
Istvan Csomortani
6fb56079ee
library/util_gtlb: Add Makefile
2015-10-16 13:58:01 +03:00
Istvan Csomortani
8ecdb4a4ca
library/tdd_control: Add common registers to the register map and fix init value of a register
...
+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
2015-10-16 11:57:54 +03:00
Istvan Csomortani
bbdc693954
pzsdr/all: Update Makefile
2015-10-16 11:57:51 +03:00