Commit Graph

6137 Commits (de70157e3a50dae3013609cdcbedf30768d103c2)

Author SHA1 Message Date
Istvan Csomortani b9a5bb3549 axi_dacfifo: Optimize the AXI read logic
Save the valid AXI beats number of the last AXI transaction, and the valid
DMA beats number of the last AXI beat, so the read back logic can use this
data and prevent to feel up the CDC memory with invalid samples. Also in
this way the end of the read back cycle get a more robust control: no more
duplicated samples at the end of the buffer.
2016-07-20 11:49:06 +03:00
Istvan Csomortani e46990e508 axi_dacfifo: Cosmetic changes
Rename a few registers and fix indentation.
2016-07-20 11:49:06 +03:00
Istvan Csomortani b48401175a axi_dacfifo: Optimize the AXI write logic 2016-07-20 11:49:06 +03:00
Rejeesh Kutty c75289be21 fmcomms11- use qpll tx-12g5, cpll rx-6g25 2016-07-19 16:21:49 -04:00
Rejeesh Kutty 74f45cff24 axi-ad9625: fix clock ratio to match sampling clock 2016-07-19 16:21:13 -04:00
Matthew Fornero aa3a821456 up_axi: Same cycle BVALID/READY fails on Altera
The Qsys interconnect does not handle the assertion of BVALID on the
same cycle as [A]WREADY. Add a single cycle of delay to prevent
deadlocks.

Similar to:
2817ccdb22
("up_axi: altera can not handle same clock assertion of arready and rvalid")

Signed-off-by: Matthew Fornero <matt.fornero@mathworks.com>
2016-07-19 09:50:43 -07:00
Shrutika Redkar d6243f3d01 update in fmcomms11 tcl and clock constrains 2016-07-18 09:04:13 -04:00
Lars-Peter Clausen b2203cacce adi_project.pl: Fix ADI_NO_BITSTREAM_COMPRESSION detection logic
Only enable bitstream compression only if both the
ADI_NO_BITSTREAM_COMPRESSION environment and TCL variable are not set.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 11:33:56 +02:00
Lars-Peter Clausen 44d9f98e12 adi_project.pl: Fix ADI_NO_BITSTREAM_COMPRESSION detection logic
Only enable bitstream compression only if both the
ADI_NO_BITSTREAM_COMPRESSION environment and TCL variable are not set.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:44:42 +02:00
Lars-Peter Clausen fe08222bdf Enable bitstream compression for Xilinx projects
Enabling bitstream compression reduces the size of the generated bitstream.

This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.

On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.

The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.

When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.

Initial tests show a reduction of a round 50% in size for most ADI
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 11:40:04 +03:00
Lars-Peter Clausen 62c7114d77 Enable bitstream compression for Xilinx projects
Enabling bitstream compression reduces the size of the generated bitstream.

This means on one hand it will consume less storage, which is especially
useful for the BOOT partition of the ADI images where we store BOOT.BIN
files for all supported platforms.

On the other hand a smaller bitstream is faster to load from the storage
medium and it is also faster to program to the FPGA. So it reduces the
overall boot time as well.

The only downside of bitstream compression is that the bitstream size is no
longer constant, but depends on the actual design and resource utilization.
This will not work with bootloaders that expect a fixed size.

When building a bitstream using the tcl scripts bitstream compression can
be disabled by setting the ADI_NO_BITSTREAM_COMPRESSION environment
variable.

Initial tests show a reduction of a round 50% in size for most ADI
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-07-14 10:16:15 +02:00
Rejeesh Kutty 1df942b752 rfifo- buffer 1 seg before read 2016-07-12 10:24:22 -04:00
AndreiGrozav 12abe2b6b9 fmcomms2: Makefile update 2016-07-12 09:39:24 +03:00
AndreiGrozav 283bf9ad75 fmcomms2_a10GX: Add fmcomms2 on a10gx 2016-07-11 18:37:18 +03:00
AndreiGrozav e9fe752b7a fmcomms2_qsys.tcl: Add fmcomms2 block design script for Altera 2016-07-11 18:34:21 +03:00
Rejeesh Kutty 4f0d7bd6eb util_wfifo: read after write is complete 2016-07-11 09:59:31 -04:00
Rejeesh Kutty 832efdc99c hdlmake updates 2016-07-08 13:58:56 -04:00
Rejeesh Kutty 7a03d44e4e adxcvr- clock buffers are removed 2016-07-08 13:57:27 -04:00
Rejeesh Kutty 20ac95b1ec adxcvr- initial commit 2016-07-08 13:57:27 -04:00
Adrian Costina 92c580a84d daq3: A10GX, updated project to the TCL flow 2016-07-08 12:00:37 +03:00
Istvan Csomortani 7be017baa3 daq1: Add AXI PLDDR FIFO to the receive path
The AD9684 has two 500 MSPS converter, the system can not handle this
throughput without a FIFO.
2016-07-07 07:15:54 +03:00
Istvan Csomortani 9169e20b5e daq1: Fix the data width on the DMAC interfaces
+ HP ports maximum width is 64 bits
+ DMAC's default width is 64, no need for redefinition
2016-07-07 07:15:54 +03:00
Rejeesh Kutty 48762519b5 make updates 2016-07-06 15:02:00 -04:00
Istvan Csomortani 427cc84bb2 axi_ad7616: Rename the physical interface signals to rx_*
No functional modification.
2016-07-01 14:45:23 +03:00
AndreiGrozav 69a68a99e0 imageon/zed - remove onboard hdmi and update design 2016-07-01 14:11:49 +03:00
Shrutika Redkar ad491ec04a updated tcl files after inclusion of ad9162 core 2016-06-30 13:26:16 -04:00
Shrutika Redkar d931b2ee64 ad9162 core verilog files 2016-06-30 10:24:01 -04:00
Adrian Costina c6c3622816 a10gx: Updated common design adding explicit clock frequency and synchronous reset deassertion 2016-06-30 10:59:29 +03:00
Istvan Csomortani 8d558b2538 make: Update Make files 2016-06-29 14:50:07 +03:00
Istvan Csomortani 18e28b01fd axi_ad7616: Add burst counter to the parallel interface
With this counter the parallel logic supports the burst sequencer.
2016-06-29 14:17:28 +03:00
Istvan Csomortani e6494b9a74 axi_ad7616: Change the DMA interface type to Write FIFO 2016-06-29 14:11:02 +03:00
Istvan Csomortani 64633e519c Merge remote-tracking branch 'origin/dev_ad7616' into dev 2016-06-29 12:32:39 +03:00
Istvan Csomortani 2e80dec513 adrv9371x/zc706: Update project with the new axi_dacfifo 2016-06-22 12:33:47 +03:00
Istvan Csomortani cdf01a492e library/axi_dacfifo: Update the bypass logic
The bypass logic is located between the AXI read controller and the
DAC CDC fifo. When the bypass is enabled the DMAC destination interface
must be clocked with the PL_DDR controller's ui_clk. This way it can easily
switch between the AXI read's stream and DMAC's stream interface.
2016-06-22 12:24:54 +03:00
Rejeesh Kutty def47dd536 interfaces: added xcvr interfaces 2016-06-17 12:00:15 -04:00
Rejeesh Kutty 36fbf4fc42 util_adxcvr: shared xcvr cores 2016-06-17 11:59:42 -04:00
Rejeesh Kutty 87cf13b0ef util_adxcvr- system verilog interfaces 2016-06-16 16:41:43 -04:00
Rejeesh Kutty 80ce7aeb66 util_adxcvr- updates 2016-06-16 16:40:57 -04:00
Istvan Csomortani 7c762f63a8 library/axi_dacfifo: Fix the control logic of the write side
Fix the control logic for the AXI write transactions.
2016-06-15 13:49:00 +03:00
Istvan Csomortani d5ce137c55 library/axi_dacfifo: Fix reset for a few registers 2016-06-15 13:49:00 +03:00
Istvan Csomortani 10090a296e library/axi_dacfifo: Cosmetic changes
Rename a few registers and improve consistency.
2016-06-15 13:49:00 +03:00
Rejeesh Kutty 67c948e821 fmcomms2/a10soc-- bad board design 2016-06-14 12:29:36 -04:00
Rejeesh Kutty 7485d27d37 ad9361/altera- device-family variable 2016-06-14 12:28:13 -04:00
Rejeesh Kutty 5d437083cc ad9361/altera- a10+ only 2016-06-14 12:19:54 -04:00
Rejeesh Kutty dc45287b14 util_adxcvr- added 2016-06-14 12:19:18 -04:00
AndreiGrozav c19ed4c8ef axi_hdmi_tx_core: Fixed embedded sync synchronization signals 2016-06-14 14:30:28 +03:00
AndreiGrozav aee38e1cc9 up_hdmi_tx: Fixed data path width 2016-06-14 14:27:03 +03:00
Shrutika Redkar 27fd5f5bdc modified prbs7 and prbs15 gereration code 2016-06-13 14:44:03 -04:00
Shrutika Redkar 83dd7e91c4 deleted pn23 and pn 31, data width yet to be modified 2016-06-13 14:44:03 -04:00
Adrian Costina 130bfdd408 motcon2_fmc: Update to revision C 2016-06-13 15:42:25 +03:00