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6137 Commits (de70157e3a50dae3013609cdcbedf30768d103c2)

Author SHA1 Message Date
Rejeesh Kutty 9e0c39a71b alt_serdes_clk- changes 2016-09-12 10:30:28 -04:00
Istvan Csomortani f4be0524b4 altera/common: Add SERDES related modules 2016-09-09 18:04:41 +03:00
Istvan Csomortani a183e51a12 axi_ad9361: Add parameter R1_MODE_EN 
R1_MODE_EN can disable the second I/Q channel of the core. This way
the user can save resources by cutting down the size of the core.
 2016-09-09 16:34:11 +03:00
Istvan Csomortani e42206e510 axi_ad9361: Add a TDD enable/disable parameter 2016-09-09 14:38:28 +03:00
Istvan Csomortani be41a8bcaa axi_ad9361: Delete debug ports of the tdd module 2016-09-09 14:38:28 +03:00
Adrian Costina 521c41ce32 adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier 2016-09-08 11:44:45 +03:00
Adrian Costina 40c9fc92c1 a10soc: Switched to tcl flow 2016-09-08 11:31:06 +03:00
Adrian Costina 0d095f5da9 a10gx: Added system_type variable in common design 2016-09-08 11:29:14 +03:00
Lars-Peter Clausen 53033a99f5 axi_dmac: Fix tlast generation on AXI stream master 
For the AXI stream interface we want to generate TLAST only at the end of
the transfer, rather than at the end of each burst.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2016-09-06 18:54:14 +03:00
Istvan Csomortani bae63ae5b1 version_upgrade: Update the DAQ3 project to 2016.2 2016-09-06 11:41:37 +03:00
Istvan Csomortani b8c34791d5 version_upgrade: fmcjesdadc1 updated to 2016.2 
Xilinx IP core JESD204 is updated to version 7.0
 2016-09-06 11:41:37 +03:00
AndreiGrozav b837883b98 pzsdr1/pzsdr1/pzsdr1_cmos_system_constr: Fixed voltage level selection 2016-09-01 17:16:59 +03:00
AndreiGrozav bbcf2a3ec3 axi_ad9434/axi_ad9434_constr: Change constraint file to resolve critical warning 2016-09-01 17:16:59 +03:00
Rejeesh Kutty 4ae084ee32 avl_adxcvr- compile fixes 2016-09-01 10:06:28 -04:00
Rejeesh Kutty 5544e3cf10 axi_adxcvr- compile fixes 2016-09-01 10:06:28 -04:00
Rejeesh Kutty 230f1526c0 avl_adxcfg- compile fixes 2016-09-01 10:06:28 -04:00
AndreiGrozav 93fa5aeec3 fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2 2016-09-01 16:11:39 +03:00
Adrian Costina dc21384002 pzsdr: Update ccpci base design 2016-09-01 09:06:30 +03:00
Rejeesh Kutty 2f9ac4a342 altera- qsys-script does not support most tcl commands 2016-08-30 11:50:36 -04:00
Rejeesh Kutty 917da79da1 altera- source defaults for qsys-script 2016-08-30 11:50:36 -04:00
Rejeesh Kutty 8192e755e1 altera- defaults 2016-08-30 11:50:36 -04:00
AndreiGrozav 1eccf5af07 fmcomms7: Update common design to Vivado 2016.2 2016-08-30 16:46:15 +03:00
AndreiGrozav 2015bcedaa fmcadc2: Update common design to Vivado 2016.2 2016-08-30 16:42:58 +03:00
Adrian Costina 6f0d124861 fmcadc5: Update to Vivado 2016.2 2016-08-30 16:09:28 +03:00
Adrian Costina 4248b9373a ad6676evb: Update to Vivado 2016.2 2016-08-30 16:08:07 +03:00
Rejeesh Kutty b7ea2efa87 altera- xcvr cores 2016-08-29 15:18:48 -04:00
AndreiGrozav a6e6b3f96e version_upgrade: Update fmcomms1 common design to Vivado 2016.2 2016-08-29 15:59:15 +03:00
AndreiGrozav 2e59f377e1 version_upgrade: Update ac701, mitx045 and zed common design to Vivado 2016.2 2016-08-29 09:50:46 +03:00
Rejeesh Kutty 9799599eee library/ad9361- add dac clk sel 2016-08-26 10:31:00 -04:00
Rejeesh Kutty 74bc498a6d library/common- added dac clock select 2016-08-26 10:31:00 -04:00
Rejeesh Kutty 271029768c pzsdr/cmos - swap==1 2016-08-26 10:31:00 -04:00
Adrian Costina d18f6aa816 adrv9371x: A10GX, added adcfifo 
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
 2016-08-26 14:46:48 +03:00
Istvan Csomortani 5cc2ab37a5 version_upgrade: Common ZC702 get an upgrade to 2016.2 
Xilinx IP Clock Wizard updated to version 5.3
 2016-08-26 10:20:04 +03:00
Istvan Csomortani cd0c981b50 projects/scripts: Fix to prevent a warning 
In case of axi_interconnects, when just one slave and master interface is
active, the 'Interconnect Optimization Strategy' is disabled. So this
parameter should be set just if there is more than one slave interface.
 2016-08-26 10:08:00 +03:00
Istvan Csomortani 6ab137a0e9 projects/scripts: Cosmetics 2016-08-26 10:07:08 +03:00
Istvan Csomortani 9dfcfe6146 version_upgrade: adv7511 common script to 2016.2 
Xilinx IP Clock Wizard updated to version 5.3
 2016-08-26 09:52:01 +03:00
Rejeesh Kutty 264bde77ad sdrstk- SWAP==1 option 2016-08-24 12:07:13 -04:00
Adrian Costina 3c6cfdc7b5 adrv9371x: A10GX, switched TX lanes 2016-08-24 18:06:14 +03:00
Adrian Costina 215edb11c6 adrv9371: A10GX, updated design 
- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
 2016-08-23 18:25:48 +03:00
Rejeesh Kutty 320f87d63b sdrstk- fix spi/port connections 2016-08-22 16:52:43 -04:00
Adrian Costina 270f8a6bbe adrv9371x: Updated project common 2016-08-22 16:58:21 +03:00
Adrian Costina f1b834ab25 scripts: Update script so that all interconnects are optimized for performance 2016-08-22 16:56:02 +03:00
Adrian Costina c6b065c349 zc706: Updated DDR3 dacfifo 2016-08-22 16:48:52 +03:00
Rejeesh Kutty f697490de6 hdlmake- updates 2016-08-19 15:59:41 -04:00
Rejeesh Kutty 5c35012f54 sdrstk- updates 2016-08-19 15:59:13 -04:00
Rejeesh Kutty 8582517712 sdrstk- updates 2016-08-19 15:56:48 -04:00
Rejeesh Kutty 67bf8f8e78 scripts- fix path and device defaults and override 2016-08-19 15:56:07 -04:00
Rejeesh Kutty 6ef9555909 sdrstk- added 2016-08-19 13:45:40 -04:00
Adrian Costina 41203d07e9 adrv9371x: A10GX, update SPI connection 2016-08-18 17:42:27 +03:00
Shrutika Redkar 10b9a0e52f upadated xcvr ips 2016-08-17 15:51:55 -04:00