591a23156b
Makefiles: Update header with the appropriate license
2021-09-16 16:50:53 +03:00
6f2f2b8626
makefile: Regenerate make files
2021-01-20 01:02:56 +02:00
acbbd4636a
sysid: Upgrade framework, header/ip are now at 2/1.1.a
...
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
...
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
a4a9d0a19d
fmcomms11/zc706: Relax core clock timing to 250MHz/125MHz
2019-06-10 11:23:41 +03:00
119fd0915a
fmcomms11: Make the lane remapping after the link layer
2019-06-10 11:23:41 +03:00
58d55f61db
fmcomms11: Add desciption how to swap memory resource for the FIFOs
2019-06-10 11:23:41 +03:00
94dc848292
fmcomms11: Move the FIFO address variables into system_bd
...
These variables can vary in function of the available memory resources
of the FPGA carrier board.
2019-06-10 11:23:41 +03:00
d9230fdc5e
fmcomms11: Connect DAC fifo bypass to a GPIO
...
GPIO[60] can be used to control the bypass line of the
util_dacfifo module.
2019-06-10 11:23:41 +03:00
c1bfd9ddab
makefile: Update fmcomms11
2019-05-29 10:23:24 +03:00
cf03e216fe
fmcomms11: Update the project with the new TPL
2019-05-16 13:26:58 +03:00
eba1975144
fmcomms11: Initial commit
2019-05-16 13:26:58 +03:00
43496cf80a
fmcomms11: Move project to a feature branch
2018-04-13 18:22:15 +03:00
377247a434
Regenerate project Makefiles using the new shared Makefile includes
...
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.
It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
425e803364
license: Fix a spelling mistake
2018-04-11 15:09:54 +03:00
502989c25f
jesd_rst_gen:constraints: Remove invalid false path definitions
...
The constraint where added to remove timing problems on the reset path.
The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.
Projects affected by this change:
- daq3
- adrv9739
- ad6676evb
- fmcadc5
- daq2/kcu105
- fmcadc2
- adrv9371x
- fmcomms11/zc706
- fmcjesdadc1
2018-04-11 15:09:54 +03:00
a740b6012f
Make: Use $(MAKE) for recursive make commands
...
This commit should resolve the issue #64 .
Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
bf3ba4426c
fmcomms11: Update the SPI IO definitions
2018-01-29 18:48:31 +02:00
55b4603e60
fmcomms11: Update the clock tree
...
- one single reference clock for both rx and tx channels
- delete the SYSREF inputs
- update the IO location of the usr_clk
2018-01-29 18:44:15 +02:00
ff562e7165
fmcomms11: Delete trailing whitespaces
2018-01-29 17:46:54 +02:00
0360e8587e
Connect JESD204 interrupts
...
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
b7ca17f02b
scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
2017-06-07 12:06:50 +03:00
50cdb6db67
Merge branch 'jesd204' into dev
2017-05-31 20:44:32 +03:00
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
85ebd3ca01
license: Update license terms in hdl source files
...
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
4d00439d52
fmcomms11: Convert to ADI JESD204
...
Convert the FMCOMMS11 project to the ADI JESD204 link layer cores. The
change is very straight forward, but a matching change on the software side
is required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
8063ba2b66
make updates
2017-03-20 16:05:18 -04:00
fb4a583613
projects/system_bd- adc/dac fifo board designs
2017-02-27 16:06:39 -05:00
c598e84258
remove processing order (no clock def dependency)
2017-02-22 16:02:08 -05:00
edd5e9570f
file renamed; sed output; fingers crossed
2017-02-22 15:56:37 -05:00
11347c49be
fmcomms11- device set to -3
2016-11-16 13:43:07 -05:00
b85a282748
fmcomms11- lane swap
2016-11-16 10:26:47 -05:00
5731ba3300
fmcomms11- xcvr updates
2016-10-24 09:51:40 -04:00
7fd9280cbf
fmcomms11- xcvr updates
2016-09-26 15:19:05 -04:00
16ee1336c3
Makefile: Update make files
2016-09-15 11:41:06 +03:00
ce1fed1ce6
dmafifo- adc/dac split
2016-08-16 12:54:39 -04:00
0cd608a7e2
lib_refactoring: Update Make files
2016-08-08 16:38:38 +03:00
df36902713
lib_refactoring: Fix path of the IO macros
2016-08-08 15:07:19 +03:00
d60bce654c
Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
2016-08-05 15:16:04 +03:00
e42b4ea378
hdlmake- updates
2016-08-04 13:28:25 -04:00
7ca8e10004
make: Update Make files
2016-08-01 14:24:48 +03:00
d6243f3d01
update in fmcomms11 tcl and clock constrains
2016-07-18 09:04:13 -04:00
48762519b5
make updates
2016-07-06 15:02:00 -04:00
ad491ec04a
updated tcl files after inclusion of ad9162 core
2016-06-30 13:26:16 -04:00
Adrian Costina
Sergiu Arpadi
Istvan Csomortani
Lars-Peter Clausen
AndreiGrozav
Rejeesh Kutty
Shrutika Redkar