Commit Graph

19 Commits (de70157e3a50dae3013609cdcbedf30768d103c2)

Author SHA1 Message Date
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Adrian Costina 98b58562d6 system_top: Non functional changes in system_tops to reduce warnings
Loop back the unused GPIO pins, and add all the SPI interface to system
wrapper instance.

The following system_top modules were changed:
  - ad738x_fmc
  - ad7616_sdz
  - ad77681evb
  - ad77681evb
  - ad7768evb
  - ad9739a_fmc
  - ad9434
  - adrv9739
  - fmcadc5
  - ad6676evb
  - ad9265
  - ad5766
  - fmcomms5
  - m2k
2018-04-11 15:09:54 +03:00
Adrian Costina c07fefcbd7 fmcadc5: Update to the ADI JESD interface 2017-11-20 15:12:47 +02:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty d29f420ffa axi_fmcadc5_sync: add a calibration signal generation 2017-04-28 11:13:24 -04:00
Rejeesh Kutty 902eaaaf4c fmcadc5- sync updates 2017-04-27 13:26:17 -04:00
Istvan Csomortani e4e5b30ade fmcadc5: Integrate ad_sysref_gen into the project 2017-01-03 13:52:39 +02:00
Rejeesh Kutty 11b57290f1 fmcadc5- replaced with axi_adxcvr 2016-11-23 16:22:05 -05:00
Rejeesh Kutty cafc80c829 fmcadc5: add programmable io delay 2015-11-02 12:10:18 -05:00
Rejeesh Kutty cb2bda48c0 fmcadc5- gt/ip updates 2015-10-19 09:31:32 -04:00
Rejeesh Kutty 08777ca566 fmcadc5- latest board changes 2015-10-15 10:46:07 -04:00
Istvan Csomortani 4f99bdd93f fmcadc5: Update project
+ Update the JESD IP core for Vivado 2015.2
+ Update the framework for JESD interface
2015-09-25 19:11:14 +03:00
Rejeesh Kutty a6cae6b477 iobuf: do is a system verilog keyword 2015-05-21 14:06:17 -04:00
Istvan Csomortani 02dfa865b4 fmcadc5_vc707: Fix system top. 2015-04-06 12:15:49 +03:00
Rejeesh Kutty d93b967980 fmcadc5: 2014.4 updates 2015-03-23 10:00:46 -04:00
Rejeesh Kutty 19e4950b72 renamed to match official names 2014-12-08 10:44:15 -05:00