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15 Commits (de70157e3a50dae3013609cdcbedf30768d103c2)

Author SHA1 Message Date
Laszlo Nagy 51b643b978 Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Sergiu Arpadi 3be5137aec cn0540/cora: Remove multicycle constraint 
Design uses 80MHz spi_clk which does not require
special considerations
 2021-02-18 14:14:16 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific 
Updated all system_project and Makefiles
 2020-11-02 16:13:35 +02:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
Sergiu Arpadi 72635d73e3 cn0540: Add axi_clkgen to Makefile 2020-10-14 00:05:57 +03:00
Sergiu Cuciurean da6d9da4f0 projects: cn0540: coraz7s: Add XADC support 
The coraz7s has an Arduino/chipKIT Shield connector with 6 Single-ended
and 8 Differential Analog inputs tied to Xilinx's XADC.
The CN0540 uses the A0-5 pins as single-ended ADC channels to monitor
the differential input, ADC driver, and buffer voltages.

Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean@analog.com>
 2020-10-02 11:14:21 +03:00
Istvan Csomortani 11822e2824 cn0540/coraz7s: Set and input delay of one spi_clk cycle for the MISO line 
Note, the current SCLK to spi_clk ratio is four. That means, the input
delay in the MISO line is 25% of the SCLK period.

If the SCLK to spi_clk ratio is changing, this constraint must be
updated.
 2020-10-02 10:50:06 +03:00
Istvan Csomortani dae1de0405 cn0540/bd: Generate a 80MHz spi_clk 
Generate a higher frequency of spi_clk using an axi_clkgen. (MMCM)

CAUTION: ad7768-1 is still violating the standard SPI timing,
reducing the timing window significantly for the last bit (or last high
bit).
 2020-10-02 10:50:06 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Istvan Csomortani 4838ac0ac2 cn0540/coraz7s: Time the SPI interface of AD7768-1 2020-09-15 18:14:23 +03:00
Istvan Csomortani d8c98c9904 cn0540/coraz7s: Relax timing in SPI Engine 2020-08-24 16:45:02 +03:00
Stanca Pop 847f0f22e6 cn0540: Fix typo 2020-06-04 18:38:14 +03:00
Stanca Pop 193fce338d cn0540: Initial commit 2020-05-28 18:49:35 +03:00