8ec657315c
adrv9009zu11eg: Drive cpack/upack reset from TPL
2022-02-07 19:14:01 +02:00
d949936a1b
adrv9009zu11eg/common: EXT_SYNC updates
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- Explicitly enable EXT_SYNC parameter for Rx/Obs
- Loopback manual sync for each TPL (we do not combine them yet because
it requires extra CDC logic)
2022-02-07 19:14:01 +02:00
b7f34f7bd9
adrv9009zu11eg & common/zcu102 : Fix zynqmp ref clock definition
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The derived clocks of the zynqmp core are not calculated correctly due
rounding issues, instead of 100MHz the value of 99999001 is received
causing warnings during system validation.
This can be fixed/worked around with the proper reference clock
definition.
2021-08-20 10:46:09 +03:00
4cf53f373b
Revert "adrv9009zu11eg: Integrate data_offload"
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This reverts commit 78999e154e
2021-08-19 21:43:09 +03:00
78999e154e
adrv9009zu11eg: Integrate data_offload
2021-08-06 11:55:24 +03:00
7be66b63c1
adrv9009zu11eg:fmcomms8: Fix lane swapping for TX channels 0 and 1 on the FMCOMMS8
2021-02-05 15:07:09 +02:00
9364c8501a
adrv9009_zu11eg: Add synchronization at application layer
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Switch RX path reset to be controlled by the TPL and use
RX SYSREF as external synchronization for the ADC TPL
Use TX SYSREF for synchornizing the TX DDS
2020-10-07 09:04:21 +03:00
c4b94fc564
adrv9009zu11eg: Add S JESD204 parameter for the projects
2020-02-18 11:19:02 +02:00
d2817863a1
adrv9009zu11eg: Add FMCOMMS8 support
2020-02-18 11:19:02 +02:00
29f18e501e
adrv9009zu11eg: Cleanup bd file
2020-02-18 11:19:02 +02:00
09ad67bfd7
adrv9009zu11eg: Make the project more parametrizable
2019-12-04 14:59:18 +02:00
0cb5c0bdaf
adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency
2019-11-27 16:27:44 +02:00
dfe3258a4f
adrv9009zu11eg: Add axi_sysid
2019-11-19 10:29:57 +02:00
a589a2c7eb
adrv9009_zu11eg_som: Change design partitioning
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Create a structure similar with ADRV936x projects
2019-11-14 15:25:23 +02:00
Laszlo Nagy
Adrian Costina
Istvan Csomortani