Commit Graph

67 Commits (de70157e3a50dae3013609cdcbedf30768d103c2)

Author SHA1 Message Date
Laszlo Nagy 5edf6c19de adrv9009/zcu102: Hook up ref clock from IBUFDS_GT 2022-02-15 11:09:37 +02:00
Laszlo Nagy 4bd55dc5c2 adrv9009/zc706: Hook up ref clock from IBUFDS_GT 2022-02-15 11:09:37 +02:00
Laszlo Nagy aac4746398 adrv9009/common/adrv9009_bd: Take ref clock from the IBUFDS_GT
In some cases (GTX2) the transceiver may gate the out_clk when it is in
reset or misconfigured. This will stop the clock generators from getting
a clock prior removing the reset of the XCVR.  The XCVR has a requirement
of running user clock while removing the reset. The correct sequence must be :

Enable device clocks (user clock)
Remove the reset from the XCVR
2022-02-15 11:09:37 +02:00
Filip Gherman 4ec8797c7c adrv9009: Parameterize JESD204 configuration values 2022-01-13 10:15:05 +02:00
Robin Getz 63b6711cfa start adding some doc to the ./projects directory
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
2021-11-10 14:01:06 +02:00
LIacob106 58c1d2e3b2 projects: fixed xcvr clocks that generated critical warning 2021-11-09 12:40:14 +02:00
LIacob106 d4126739b4 projects: remove hardcoded div_clk from xcvr 2021-10-27 12:11:22 +03:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
Istvan Csomortani d539a8119c adrv9009/intel: Fix fPLL configuration
When phase alignment is active, the PFD frequency value should be used
as outclk1 actual frequency.

The configuration interface of the fPLL does not support fractional values.
If the reference clock is fractional, the tool will throw an error that requirement
above is not respected.

Round up the reference clock for the SERDES and the lane rate in order to
overcome this issue, until it's not fixed by Intel.
2021-01-12 19:34:44 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Adrian Costina 144fcc2965 adrv9009: Fix typo for number of samples calculation for observation channel 2020-09-25 11:58:58 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Dragos Bogdan c8e0a1ec04 projects: adrv9009: intel: Update JESD204 LANE_RATE and REFCLK_FREQUENCY
To match the Linux default setup.

Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
2020-09-09 14:15:37 +03:00
Istvan Csomortani 46b6bf8f8a adrv9009/qsys: input pipline active for jesd204_rx and jesd204_rx_os 2020-09-09 14:15:37 +03:00
Istvan Csomortani 5a8f277253 adrv9009/s10soc: Add support for Stratix10 SOC 2020-09-09 14:15:37 +03:00
Istvan Csomortani eb8e1142cd adrv9009/intel: Fix the register address layout
The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
2020-09-09 14:15:37 +03:00
Istvan Csomortani 8818089015 a10soc: Reconfiguration interface address width improvement
The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
2020-09-09 14:15:37 +03:00
Istvan Csomortani a66029aef3 adrv9009/a10gx: Delete redundant timing constraints 2020-08-11 10:14:18 +03:00
Istvan Csomortani 02ada3bbf7 a10gx: Delete input/output delay definitions
All input and output delays should be referenced to a virtual clock.

If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
2020-08-11 10:14:18 +03:00
Istvan Csomortani 71d500bdd4 adrv9009/intel: Use generic TPL cores 2020-05-26 16:22:30 +03:00
Istvan Csomortani 32eeedb660 makefile: Update makefiles 2020-05-07 08:41:49 +01:00
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
AndreiGrozav 78afe38a3f adrv9009: Add decimation and interpolation filters 2019-08-20 16:24:47 +03:00
AndreiGrozav 36a1767329 Add generic fir filters processes for RF projects 2019-08-20 16:24:47 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Istvan Csomortani 6e6f1347d7 project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
Istvan Csomortani 424abe0c02 adrv9009: DMA should use $sys_dma_resetn 2019-06-13 10:59:43 +03:00
Istvan Csomortani 0e750bea42 adrv9009: Fix dma_clk tree 2019-06-11 18:13:06 +03:00
Istvan Csomortani 7960b00684 block_design: Update with new clock net variables
Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
Istvan Csomortani 70b7d69ff8 whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
Istvan Csomortani 391ac468a7 adrv9009/common: Fix ad_xcvrcon proc call
The process ad_xcvrcon has a device_clk attribute which can be used to
connect a custom device clock to the XCVR. Fix the proc call so we can
simplify the block design script.
2019-05-29 10:27:16 +03:00
Laszlo Nagy c930395773 adrv9009:qsys: use bundled AXIS interface 2019-05-16 13:27:19 +03:00
AndreiGrozav d894c30c2d Remove deprecated/unused parameters
adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
2019-03-30 11:26:11 +02:00
Laszlo Nagy 3183fbf226 adrv9009: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy 0b66b39352 adrv9009/zc706: make SPI selection consistent 2018-12-21 17:32:48 +02:00
Laszlo Nagy 3d7a376f8b Makefile: update makefiles 2018-12-21 17:32:48 +02:00
Laszlo Nagy c9f1c92eaa adrv9009: use generic TPL
Make the block design parametrizable.
Limitations:
  F = 1,2,4
2018-12-21 17:32:48 +02:00
Laszlo Nagy 47093775ae adrv9009/zc706: top level cleanup 2018-12-21 17:32:48 +02:00
Laszlo Nagy 8adc285eab adrv9009/zc706: fix location constraints 2018-12-21 17:32:48 +02:00
Laszlo Nagy 7a5a8c5340 Revert "adrv9009: Removed ZC706 based project"
This reverts commit 7e7f75c0270bb6793bedb339f62b67bab9d77a6e.
2018-12-21 17:32:48 +02:00
Adrian Costina e09f3290ff adrv9009: Move intel project to upack2/cpack2 2018-12-03 12:23:24 +00:00
Lars-Peter Clausen 2462f8e50f adrv9009: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Adrian Costina 401395cdd1 adrv9009: A10GX: Initial commit 2018-11-27 15:31:21 +02:00