pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Adrian Costina	591a23156b	Makefiles: Update header with the appropriate license	2021-09-16 16:50:53 +03:00
Sergiu Arpadi	6f2f2b8626	makefile: Regenerate make files	2021-01-20 01:02:56 +02:00
hotoleanudan	1c208c01d6	ad9656:Add reference design for the ad9656 eval board (#494 ) Added reference design for the ad9656 evaluation board coupled with the zcu102 carrier board. The JESD204 communication link that transfers data from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1, F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>	2020-10-06 09:53:40 +03:00

Author

SHA1

Message

Date

Adrian Costina

591a23156b

Makefiles: Update header with the appropriate license

2021-09-16 16:50:53 +03:00

Sergiu Arpadi

6f2f2b8626

makefile: Regenerate make files

2021-01-20 01:02:56 +02:00

hotoleanudan

1c208c01d6

ad9656:Add reference design for the ad9656 eval board (#494 )

Added reference design for the ad9656 evaluation board coupled with the
zcu102 carrier board. The JESD204 communication link that transfers data
from the 4 ADCs to the FPGA has the following paramenters : L=4, M=4, S=1,
F=2, HD=0, N=16, NP=16. The JESD204 line rate is configured to be 2.5GHz.

Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>

2020-10-06 09:53:40 +03:00

3 Commits (de70157e3a50dae3013609cdcbedf30768d103c2)