Commit Graph

18 Commits (ddd8a14790df3a00ae204ca3a6b728f057a49d82)

Author SHA1 Message Date
Adrian Costina 83cebe899f daq3: Update projects to the new TPL
Also modified the FIFO ports to have the same widths so that in a
future commit the bypass would be available for cases when the
sampling rate won't be the maximum rate or the number of channels
active will be less than maximum number of channels
2020-10-21 18:59:37 +03:00
Istvan Csomortani 9ee0f09078 daq3:qsys: Activate input pipeline stage for AD9680's JESD interface 2020-09-09 14:15:37 +03:00
Laszlo Nagy 6c6d14722d daq3:qsys: use bundled AXIS interface 2019-05-16 13:27:19 +03:00
Laszlo Nagy 7f16f823ff Revert "axi_dmac: add tlast to the axis interface for Intel"
This reverts commit e2c75c015f.
2019-05-16 13:27:19 +03:00
Laszlo Nagy 27f1e4eaed daq3: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Laszlo Nagy d8e11cfce5 daq2/3: update DAC TPL base addresses
The TPL for DACs can be relocated to addresses which match the software
expectations.
2018-12-04 14:02:22 +02:00
Lars-Peter Clausen 1375dcfeaa daq3: Use new pack/unpack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Laszlo Nagy e2c75c015f axi_dmac: add tlast to the axis interface for Intel
This change adds the TLAST signal to the AXI streaming interface
of the source side for Intel targets.
Xilinx based designs already have this since the tlast is part of the
interface definition.

In order to make the signal optional and let the tool connect a
default value to the it, the USE_TLAST_SRC/DEST parameter is
added to the configuration UI. This conditions the tlast port on
the interface of the DMAC.

Xilinx handles the optional signals much better so the parameter
is not required there.
2018-07-06 16:30:30 +03:00
Adrian Costina f692d7bc40 daq3: Disable start synchronization for the ADC DMA
The ADC FIFO does not provide any sync output and for two channels it's not needed
2017-11-01 09:31:19 +02:00
Adrian Costina fe1adb6e4f daq3: A10GX, updated to the ADI JESD204
- changed lane rate to 12.33Gbps
- added dac fifo
2017-10-25 14:45:27 +01:00
Lars-Peter Clausen 69a23ecde3 avl_adxcvr: Simplify TX lane mapping
Currently the TX lane mapping is implemented by having to connect tx_phy_s_* to
the tx_ip_s_* and the tx_phy_d_* to the tx_ip_d_* signals in the system
qsys file in the desired order.

Re-work things so that instead the lane mapping is provided through the
TX_LANE_MAP parameter. The parameter specifies in which order logical lanes
are mapped onto the physical lanes.

The appropriate connections are than made inside the core according to this
parameter rather than having to manually connect the signals externally.

In order to generate a 1-to-1 mapping the TX_LANE_MAP parameter can be left
empty.

This change slightly reduces the boiler-plate code that is necessary to
setup the transceiver.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-03 17:57:58 +02:00
Lars-Peter Clausen f0655e63a6 avl_adxcvr: Derive PLL and core clock frequency from lane rate
The PLL frequency must be half of the lane rate and the core clock rate
must be lane rate divided by 40. There is no other option, otherwise things
wont work.

Instead of having to manually specify PLL and core clock frequency derive
them in the transceiver script. This reduces the risk of accidental
misconfiguration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
Rejeesh Kutty 56867b362e daq3- updated to 12.5G 2017-06-16 09:02:26 -04:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Istvan Csomortani fcd56a2f90 daq3/a10gx: Update project to the new GT framework
- Update common script
- Update system_top, some port names were changed
- Update constraint files
2016-10-10 16:22:08 +03:00
Istvan Csomortani 9ace02a227 daq3/a10gx: Update project to the new GT framework 2016-10-06 10:25:25 +03:00
Adrian Costina 999eccc134 daq3: Update A10GX project to Quartus 16.0 2016-08-01 16:19:43 +03:00
Adrian Costina 92c580a84d daq3: A10GX, updated project to the TCL flow 2016-07-08 12:00:37 +03:00