Commit Graph

4507 Commits (dd6983647303771e63dc55d3546da63d2d7f636d)

Author SHA1 Message Date
Adrian Costina dd69836473 util_dacfifo: Infer clock and reset signals 2018-04-11 15:09:54 +03:00
Adrian Costina 3436210429 axi_adcfifo: Infer clock and reset signals 2018-04-11 15:09:54 +03:00
Lars-Peter Clausen b7f8345f17 library: Remove unreferenced files from IP file lists
Some IP core have files in their file list for common modules that are not
used by the IP itself. Remove those.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 0f443f4779 project-*.mk Update CLEAN targets 2018-04-11 15:09:54 +03:00
Lars-Peter Clausen dec0661f87 Move Xilinx specific DC filter implementation to library/xilinx/common/
The DC filter implementation in library/common/dc_filter.v is Xilinx
specific as it uses the Xilinx DSP48 hard-macro. There is a matching Altera
specific implementation in library/altera/common/dc_filter.v.

Move the Xilinx specific implementation from the generic common folder to
the Xilinx specific common folder in library/xilinx/common/ since that is
where all other Xilinx specific common modules reside.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 89ad5f7836 Makefile: Change IP component dependency to component definition file
Currently the IP component dependency in the Makefile system is the Vivado
project file. The project file is only a intermediary product in producing
the IP component definition file.

If building the component definition file fails or the process is aborted
half way through it is possible that the Vivado project file for the IP
component exists, but the IP component definition file does not.

In this case there will be no attempt to build the IP component definition
file when building a project that has a dependency on the IP component.
Building the project will fail in this case.

To avoid this update the Makefile rules so that the IP component definition
file is used as the dependency. In this case the IP component will be
re-build if the component definition file does not exist, even if the
project file exists.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 0048cc350e Makefile: Don't create invalid sub-project targets
At the moment targets are created for any file that is in a sub-directory
of the project directory. This is not the intended behavior. Targets should
only be generated for sub-projects. We can identify those by filtering for
sub-directories that have a Makefile.

E.g. some of those invalid targets were "adv7511.Makefile" and
"scripts.adi_board.tcl".

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 685f2eaf1e Makefile: Simplify sub-project target generation
Rewrite the sub-project targets without using $(shell) or $(eval) as they
are not required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen d5040d87ad Makefile: Update outdated example
The project the help text uses as its example does no longer exist. Replace
it with a different project.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 35a39ba2e6 Regenerate library Makefiles using the new shared Makefile include
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 2b108c63db Add common library Makefile
The library Makefiles for share most of their code.  The only difference is
the list of project dependencies.

Create a file that has the common parts and can be included
by the library Makefiles.

This drastically reduces the size of the library Makefiles and also allows
to change the Makefile implementation without having to re-generate all
Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen b20714bae2 Regenerate project top-level Makefiles
Removes a lot of boilerplate code.

Using the new scheme it is possible to add new projects or sub-projects
without having to re-generate any existing Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 297940d5d9 Add shared project top-level Makefile
The project top-level Makefile accept the all, clean and clean-all targets
and forward them to their sub-projects.

Create a common Makefile include that can be used to implement this
behavior. The shared Makefile collects all sub-directories that have a
Makefile and then forwards the all, clean and clean-all targets to them.

This is implemented by creating virtual targets for each combination of
sub-project and all, clean, clean-all targets in the form of
"$project/all", ... These virtual sub-targets are then listed as the
prerequisites of the project top-level Makefile targets.

This means there is no longer a need to re-generate top-level Makefiles
when a new project or sub-project is added.

It will also allow to remove a lot of boilerplate code.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 377247a434 Regenerate project Makefiles using the new shared Makefile includes
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 5272ed4eea Add common project Makefile for Xilinx projects
The project Makefiles for the Xilinx projects share most of their code. The
only difference is the list of project dependencies.

Create a file that has the common parts and can be included by the project
Makefiles.

This drastically reduces the size of the project Makefiles and also allows
to change the Makefile implementation without having to re-generate all
Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen ec6128dd91 Add common project Makefile for Altera projects
The project Makefiles for the Altera projects share most of their code. The
only difference is the list of project dependencies.

Create a file that has the common parts and can be included by the project
Makefiles.

This drastically reduces the size of the project Makefiles and also allows
to change the Makefile implementation without having to re-generate all
Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 8a2a394790 Remove unused projects/common/Makefile
This file only references a subdirect that no longer exists, but nothing
else.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 318dcbb5d9 adrv9371x: Set up the defualt clock output control
The TX side runs on QPLL, and the RX and RX_OS runs on CPLL by default.
The OUTCLK frequency is the same as the REFCLK.

The main reason of this modification is that the links should come up
without any DPR access, after power up, using the default reference clock
configuration (122.88 MHz).
2018-04-11 15:09:54 +03:00
Istvan Csomortani 8b671fa7ae ad77681evb: Add upscaler to the data path 2018-04-11 15:09:54 +03:00
Istvan Csomortani e782ed06cb adaq7980: Expouse the ADC sampling rate in system_bd.tcl
This way the user do not need to modify the block design, just
set the required rate in system_bd.tcl.

This commit does not contain any functional changes.
2018-04-11 15:09:54 +03:00
Laszlo Nagy bfc8ec28c3 util_axis_fifo: instantiate block ram in async mode
In cases when a shallow FIFO is requested the synthesizer infers distributed RAM
instead of block RAMs. This can be an issue when the clocks of the FIFO are
asynchronous since a timing path is created though the LUTs which implement the
memory, resulting in timing failures. Ignoring timing through the path is not a
solution since would lead to metastability.
This does not happens with block RAMs.

The solution is to use the ad_mem (block RAM) in case of async clocks and letting
the synthesizer do it's job in case of sync clocks for optimal resource utilization.
2018-04-11 15:09:54 +03:00
AndreiGrozav 51380fbea4 daq3/kcu105: Define transceiver type as Ultrascale
When software configures the system it takes into account the transceiver type.
By default, the XCVR_TYPE is 0 for 7 Series.
2018-04-11 15:09:54 +03:00
Rejeesh Kutty 8e042193be DE10: Initial commit
These modifications were taken from the old dev branch.
2018-04-11 15:09:54 +03:00
Adrian Costina 8c964389f6 sidekiqz2: Initial commit 2018-04-11 15:09:54 +03:00
Istvan Csomortani 9a44ab921b adrv9371: Swap CSN lines to preserve consistency 2018-04-11 15:09:54 +03:00
Istvan Csomortani 3277ea4be0 ad_dcfilter: Enable output registers in DSP48E1
Pipelining the DSP48 output will improve performance and often saves power so
it is suggested whenever possible to fully pipeline this function.
2018-04-11 15:09:54 +03:00
Istvan Csomortani 7824f79fc0 adrv9371x:zcu102: Use explicit PACKAGE_PIN definitions for JESD204 lanes and reference clocks 2018-04-11 15:09:54 +03:00
Istvan Csomortani 09a6eb5360 up_dac_common: Explicitly define boolean parameter as a 1 bit value 2018-04-11 15:09:54 +03:00
Istvan Csomortani a1e2b60cb3 ad_xcvr_rx_if: rx_ip_sof_d register has a width of 4 bits 2018-04-11 15:09:54 +03:00
Istvan Csomortani b6770effc5 avl_dacfifo: Add missing wire declaration 2018-04-11 15:09:54 +03:00
Istvan Csomortani f100a6bf21 avl_dacfifo: Delete deprecated false path definition 2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
Istvan Csomortani 34994222b4 license: Update old license headers 2018-04-11 15:09:54 +03:00
Laszlo Nagy ee79ba5686 axi_hdmi_tx: removed unused registers 2018-04-11 15:09:54 +03:00
Istvan Csomortani 9a76bd4536 axi_adxcvr: Set the init value of the configuration registers 2018-04-11 15:09:54 +03:00
Istvan Csomortani 571b721274 util_adxcvr: CPLLPD should be used for reset
For CPLL reset the CPLLPD ports should be used, instead of the
CPLLRESET. The recommended reset width is above 2us.
See UG576 pg. 60 for more detail.
2018-04-11 15:09:54 +03:00
Istvan Csomortani 4e60f15e7f axi_clkgen: Add a parameter to control the clock source options
Add a parameter to the control the clock source option of the MMCM. If
the MMCM has only one clock source the CLKSEL pin will be tied to VDD.

The previous version added a redundant path between the CLKSEL port and
register map.
2018-04-11 15:09:54 +03:00
Istvan Csomortani bd8c71c2ec adrv9371x:zcu102: Set DEVICE_TYPE to ultrascale 2018-04-11 15:09:54 +03:00
Istvan Csomortani d1b91c6019 fmcadc2: Delete redundant settings
This project has only receive paths, all transmit related setting of the
transceivers are redundant.
2018-04-11 15:09:54 +03:00
Istvan Csomortani f565818ab2 adi_xilinx_msg: eth_avb is not used by our designs 2018-04-11 15:09:54 +03:00
Rejeesh Kutty 72431ff952 a10soc: Connect AXI register reset 2018-04-11 15:09:54 +03:00
Adrian Costina a5407702bb util_adxcvr: Don't show reset ports for disabled lanes 2018-04-11 15:09:54 +03:00
Laszlo Nagy 0d01c08b00 util_[c|u]pack_dsf: clear syntehsis warnings
Remove unused registers and move register definitions to the generate block
that is actually using it.
2018-04-11 15:09:54 +03:00
Laszlo Nagy bce0cf8e22 util_[w|r]fifo: Reduce synthesis warnings 2018-04-11 15:09:54 +03:00
Laszlo Nagy eedd8ed5d8 up_delay_cntrl: Fix synthesis warnings, no functional changes
Reduce the number of synthesis warnings with the help of a generate
statement. When the block is disabled do not generate any logic.
2018-04-11 15:09:54 +03:00
Laszlo Nagy b4ab639db5 up_[adc|dac]_common: Define the DPR registers only when the interface is enabled 2018-04-11 15:09:54 +03:00
Laszlo Nagy 5cba46165a axi_dmac: fix synthesis warnings
Separated the 2D transfer registers to a separate generate block
2018-04-11 15:09:54 +03:00
Adrian Costina c0184bce59 adrv9379: Fix lane assignment, according to schematic 2018-04-11 15:09:54 +03:00
Laszlo Nagy 4bcf45a17a common: clean up synthesis warnings
Removed unused registers and define registers only when they are in use.
2018-04-11 15:09:54 +03:00
Laszlo Nagy b6d2def504 axi_ad9361: clear synthesis warnings
Defined the delay registers only when they are used.
2018-04-11 15:09:54 +03:00