Commit Graph

5811 Commits (dc186645d879837d584f01d13c7ba830bfa10dad)

Author SHA1 Message Date
Istvan Csomortani b0a5be8565 axi_ad9122: Add loaden port for altera support 2016-12-06 15:24:20 +02:00
Istvan Csomortani cedca30cd6 axi_ad9122: Update hw tcl script for altera 2016-12-06 15:24:19 +02:00
Istvan Csomortani 0715c962f1 altera/ad_serdes: Fix net alignment for rx_out at ad_serdes_in 2016-12-06 15:24:19 +02:00
Istvan Csomortani 6cf9df50e3 altera/ad_serdes: Define DEVICE_FAMILY in hw script 2016-12-06 15:24:18 +02:00
Adrian Costina 7a8dc92b84 usb_fx3: Add interrupt monitor and increase ILA data depth 2016-12-06 11:55:28 +02:00
Adrian Costina 1e4bdea80c usrpe31x: Fix Makefile 2016-12-06 11:07:42 +02:00
Rejeesh Kutty fb585e9219 daq2/kcu105- intc configurations 2016-12-05 12:02:32 -05:00
Rejeesh Kutty 4b7bf422ee pzsdr2/ccbox- remove imu intr on pl 2016-12-05 10:21:42 -05:00
Rejeesh Kutty 351811e13f pzsdrx/ccbox- imu intr on gpio 2016-12-05 10:18:40 -05:00
Istvan Csomortani 8b8c37e2e2 scripts/adi_ip: Remove AXIMM inference from adi_ip_infer_interfaces
The AXI Memory Map interface is infered in the adi_ip_properties process.
Infer it again in the adi_ip_infer_interfaces brakes the flow,
the tool will not find the cell's address segment, so there will not be
any address space assigned to the AXI interface.
Affected cores were axi_i2s_adi and axi_spdif_tx.
2016-12-05 14:33:39 +02:00
Lars-Peter Clausen 753f4bd06e axi_intr_monitor: Slightly modify counter start points
Start the counter_to_interrupt_cnt counter when the counter_to_interrupt
value is written to the register map. This gives applications better
control over when the counter starts counting.

Also start the counter_from_interrupt on the rising edge of the interrupt
signal to avoid bogus values.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-12-02 20:09:29 +01:00
Rejeesh Kutty 8651b7d1e9 fmcjesdadc1/a5soc- 15.1 updates 2016-12-02 13:41:14 -05:00
Rejeesh Kutty 08b84dc475 adv7511_kc705- enable interconnect pipelines on hdmi dma 2016-12-02 13:40:13 -05:00
Lars-Peter Clausen 334ce5ddc0 axi_intr_monitor: Fully register IRQ output signal
The IRQ signal goes to a asynchronous domain. In order to avoid glitches to
be observed in that domain make sure that the output signal is fully
registered.

This means that the IRQ signal is no longer mask when the control enable
bit is not set. Instead modify the code to clear the interrupt when the
control enable bit is not set. This turns it into a true reset for the
internal state.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-12-02 19:28:13 +01:00
Rejeesh Kutty 1e7ab4d708 kcu105- axi-interconnect register slices 2016-12-02 11:54:04 -05:00
Rejeesh Kutty 170c781d02 hdlmake.pl- updates 2016-12-01 13:52:11 -05:00
Rejeesh Kutty 95a2e02800 library/makefile- updates 2016-12-01 13:47:02 -05:00
Adrian Costina 6e89ac3d65 pzsdr2: ccusb_lvds, add flag_a,flag_b signals 2016-11-30 17:39:02 +02:00
Adrian Costina 0faa1ebff2 pzsdr1: ccusb_lvds, add flag_a,flag_b signals 2016-11-30 17:38:04 +02:00
Lars-Peter Clausen 84a76b9dea imageon: Invert HDMI TX clock
The ADV7511 samples the parallel data bus at the rising edge of sample
clock. Generate the clock so that the falling edge is aligned to updating
the bus data. This creates larger timing margins on each side of the
sampling edge and makes the design more robust.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 15:43:24 +01:00
Lars-Peter Clausen 24cc8d284b imageon: Increase RX DMA FIFO size
Increase the RX DMA FIFO to be able to better compensate for momentarily
memory bus contention. This has shown to resolve occasional overflows that
would occur under high system memory load.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
Lars-Peter Clausen 99dae73d96 imageon: Connect hdmi_rx_core output clock to DMA
Connect the HDMI RX core output clock to the DMA rather than connecting the
HDMI RX input clock directly. This will allow the HDMI RX core to modify
the clock and e.g. insert clock buffers or similar.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
Lars-Peter Clausen 07217740b5 imageon: Increase HDMI RX clock constraint
The ADV7611 is rated for a maximum clock rate of 165MHz. Increase the clock rate constraint to match this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-11-29 14:12:39 +01:00
Adrian Costina 284fbac571 usdrx1: Xcvr updates, so that the channel parameters are correctly configured from boot time 2016-11-28 14:16:07 +02:00
Adrian Costina 45fd4f806d fmcjesdadc1: Fixed RX_PMA_CFG parameter 2016-11-25 16:33:58 +02:00
Adrian Costina 609b01f9e4 util_clkdiv: Added division by 2 option 2016-11-24 16:01:37 +02:00
Adrian Costina 91ee4394e4 axi_intr_monitor: Initial commit 2016-11-24 15:19:36 +02:00
Istvan Csomortani f03675cdab axi_dmac: ID_WIDTH must be clog2(FIFO_SIZE*2) 2016-11-24 13:20:45 +02:00
Istvan Csomortani c705623101 axi_dmac: Fix port connection and port width mismatch 2016-11-24 12:01:45 +02:00
Rejeesh Kutty 11b57290f1 fmcadc5- replaced with axi_adxcvr 2016-11-23 16:22:05 -05:00
Rejeesh Kutty 22e230618c scripts/adi_board.tcl- support multiple xcvrs 2016-11-23 16:22:05 -05:00
Rejeesh Kutty 862bd7ef2c daq3/zc706- xcvr changes 2016-11-23 15:02:20 -05:00
Rejeesh Kutty 4e3e623530 pzsdr2/ccpci- updates 2016-11-23 14:02:59 -05:00
Rejeesh Kutty 025420d6f8 library/axi_xcvrlb- xcvr changes 2016-11-23 12:00:13 -05:00
Rejeesh Kutty e5d3bae54d projects/ad6676-adrv9371: xcvr updates 2016-11-23 11:06:22 -05:00
Rejeesh Kutty daa3df4b96 projects/- xcvr updates 2016-11-22 16:23:05 -05:00
Rejeesh Kutty 8f562fd069 xcvr updates- board procedure 2016-11-22 14:43:36 -05:00
Rejeesh Kutty b1a9bd96f1 daq2: xcvr pll changes 2016-11-22 12:53:29 -05:00
Rejeesh Kutty 750b23621b board-tcl: xcvr qpll/cpll changes 2016-11-22 12:53:02 -05:00
Rejeesh Kutty 2ea997c3d5 interfaces- remove channel based pll reset 2016-11-22 11:34:29 -05:00
Rejeesh Kutty 3dbed492b3 util_adxcvr: expose cpll/qpll as it is 2016-11-22 11:32:37 -05:00
Rejeesh Kutty 3cbe735bd8 util_adxcvr: regenerate from script 2016-11-22 11:21:04 -05:00
Rejeesh Kutty c57ffc9364 axi_adxcvr- separate pll reset from channels 2016-11-22 11:12:54 -05:00
Istvan Csomortani b9795c7033 xilinx/util_adxcvr: Update enablement dependencies 2016-11-22 17:33:40 +02:00
Rejeesh Kutty 4ed7469286 fmcadc4/zc706- updates 2016-11-22 10:32:05 -05:00
Adrian Costina 8c4279f618 pzsdr1: Added ccusb_lvds initial project 2016-11-22 16:58:34 +02:00
Adrian Costina 3d0049d274 pzsdr2: ccusb_lvdsr, updated project for the latest schematic 2016-11-22 16:55:52 +02:00
AndreiGrozav aff45eae5f fmcadc2: xcvr updates 2016-11-21 18:45:38 +02:00
Rejeesh Kutty 69ee410d3d fmcomms2/zc706pr- bypass pr as default 2016-11-21 09:45:10 -05:00
Rejeesh Kutty 4739d05269 zc706pr/common- removed 2016-11-18 14:52:39 -05:00