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5811 Commits (dc186645d879837d584f01d13c7ba830bfa10dad)

Author SHA1 Message Date
Istvan Csomortani a48c4a41bc Merge branch 'hdl_2016_r2' into dev 2016-12-19 15:41:03 +00:00
Istvan Csomortani 180c96bcde Update .gitignore 2016-12-19 15:37:05 +00:00
Istvan Csomortani da7f4608a8 fmcjesdadc1/usdrx1: Clean up the mess 
Delete accidentally commited generated files.
 2016-12-19 15:35:20 +00:00
Istvan Csomortani 468214fd34 Merge branch 'hdl_2016_r2' into dev 2016-12-19 14:43:52 +00:00
Istvan Csomortani f47863bbcf usdrx1: Integrate ad_syref_gen into the project 2016-12-19 14:36:01 +00:00
Istvan Csomortani 8d799d0316 fmcjesdadc1: Intergrate ad_sysref_gen into project 2016-12-19 13:37:29 +00:00
Istvan Csomortani 0c42e04bc3 fmcadc2: Integrate ad_sysref_gen into the project 2016-12-19 12:16:05 +00:00
Istvan Csomortani 67390c2a95 ad6676evb: Update projects with ad_sysref_gen 2016-12-19 10:52:25 +00:00
Istvan Csomortani a228c05bd3 common: Add a SYSREF generation module 
The SYSREF generator is using a simple free running counter,
which runs on the JESD204 core clock. The period can be
configured using a parameter, it must respect the constraints
defined by the JESD204 standard.
The generator can be enabled through a GPIO line.
 2016-12-17 11:12:10 +02:00
Istvan Csomortani dc70807de2 Merge branch 'hdl_2016_r2' into dev 2016-12-16 16:21:09 +00:00
Adrian Costina 8879218502 a5gte: Fixed timing violations 2016-12-16 15:37:51 +02:00
Istvan Csomortani 596d0fa3fb axi_ad9122: Add a constraint for a false path 2016-12-16 12:07:40 +00:00
Istvan Csomortani a00d9870be axi_ip_constr: Fix constraints 
Modify a contraint for a false path, so it will be applied to
up_delay_cntr module too.
 2016-12-16 12:01:38 +00:00
Istvan Csomortani c0b0f9b7e9 ad6676evb: Connect SYS_REF to GPIO 2016-12-14 17:55:50 +02:00
Istvan Csomortani 557efed5d9 ad6676evb: Update clock constraints 2016-12-14 17:55:49 +02:00
Istvan Csomortani 3a2c889115 ad6676evb: Update GT configuration 2016-12-14 17:55:49 +02:00
AndreiGrozav 905c7ccf99 Merge branch 'hdl_2016_r2' into dev 
Merging commmits : c455d2d, 8846141, 1515b6f, d5165ca, d962614
 2016-12-13 19:48:47 +02:00
AndreiGrozav d962614000 usdrx1/zc706: Disabele axi_spi constraint file 
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
 2016-12-13 19:23:51 +02:00
AndreiGrozav d5165ca81f motcon_fmc: Tie unused pins to GND 2016-12-13 19:20:13 +02:00
AndreiGrozav 1515b6f1af fmcomms7/zc706: Disabele axi_spi constraint file 
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
 2016-12-13 19:18:18 +02:00
AndreiGrozav 8846141467 fmcomms1/kc705: Disabele axi_spi constraint file 
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
 2016-12-13 19:16:31 +02:00
AndreiGrozav c455d2d64f fmcadc2/vc707: Disabele axi_spi constraint file 
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
 2016-12-13 19:15:44 +02:00
Adrian Costina 9fb7db97da a5gte: Fixed timing violations 2016-12-13 10:30:24 +02:00
Istvan Csomortani ace09eb26e Merge branch 'hdl_2016_r1' into master 2016-12-12 15:13:47 +02:00
Istvan Csomortani 99f72a9b3b util_gtlb: this core is obsoleted 
The util_gtlb core is obsoleted by xilinx/axi_xcvrlb
 2016-12-12 14:23:47 +02:00
Istvan Csomortani 5c8dde8483 util_jesd_gt: this core is obsoleted 
The util_jesd_gt core is obsoleted by xilinx/util_adxcvr and altera/avl_adxcvr
 2016-12-12 14:15:38 +02:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
Istvan 06aab8ebbd pzsdr1: Set the device core to 1R1T mode 2016-12-09 16:35:46 +02:00
AndreiGrozav 8e69c838e1 common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND 2016-12-09 13:54:39 +02:00
Istvan 23c91ca48a pzsdr1/lvds: The interface runs at max 122.88 MHz 2016-12-09 11:45:11 +02:00
Rejeesh Kutty f799c40cf0 usdrx1/a5gt- xcvr interface changes 2016-12-08 16:05:23 -05:00
Rejeesh Kutty 854cd44026 ad9671- xcvr interface changes 2016-12-08 16:05:23 -05:00
Rejeesh Kutty c114888956 usdrx1- updates 2016-12-08 16:05:23 -05:00
AndreiGrozav b0eff57b0f fmcomms2/zc702: Fix critical warnings 2016-12-08 19:54:52 +02:00
AndreiGrozav 3dceb53984 fmcadc2/vc707: Fix timing violations 2016-12-08 19:51:18 +02:00
Istvan 252c67ceff fmcomms6: Delete project 
This project will not be supported in further releases.
 2016-12-08 17:22:41 +02:00
Rejeesh Kutty fb287d0178 kcu105- updates to match xilinx trd 2016-12-08 09:32:33 -05:00
AndreiGrozav 3bc9df4c51 fmcomms5: Fixed the wornings created by TDD missing connections to axi_ad9361 core 2016-12-07 21:43:19 +02:00
AndreiGrozav 8eaae98728 fmcadc2: Updates 2016-12-07 21:43:19 +02:00
Rejeesh Kutty 801da3cb25 daq3/kcu105- fix timing violations 2016-12-06 12:31:40 -05:00
Rejeesh Kutty 2d7fb03b93 adrv9371x/a10gx- fix os xcvr parameters 2016-12-06 12:31:40 -05:00
Istvan Csomortani ad96c5e881 daq3/zc706: Change the speed grade of the FPGA to 3 2016-12-06 15:24:23 +02:00
Istvan Csomortani 8f94103f8b daq1/a10gx: Makefile fix 2016-12-06 15:24:23 +02:00
Istvan Csomortani 95ee7c093c daq1/a10gx: Update system_bd port names 2016-12-06 15:24:23 +02:00
Istvan Csomortani b7143a7a3b daq1/a10gx: Update IO pin assignments 2016-12-06 15:24:22 +02:00
Istvan Csomortani a415625069 daq1/a10gx: Add spi wrapper file to the project 2016-12-06 15:24:22 +02:00
Istvan Csomortani e30a80fda0 daq1_spi: Delete device specific macro instantiation 2016-12-06 15:24:21 +02:00
Istvan Csomortani 977e6d9189 adi_ip_alt: Fix some typo 2016-12-06 15:24:21 +02:00
Istvan Csomortani 7876c8ffa4 axi_ad9684: Add loaden and phase ports for altera support 2016-12-06 15:24:20 +02:00
Istvan Csomortani a7d3df8757 axi_ad9684: Update hw tcl script for altera 2016-12-06 15:24:20 +02:00