Rejeesh Kutty
|
173837f5b2
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altera- altera ip interfaces has no consistency
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2017-06-09 16:21:44 -04:00 |
|
Rejeesh Kutty
|
74f9a99655
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fmcjesdadc1/a5gt- altera 16.1 updates
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2017-06-09 16:20:49 -04:00 |
|
Rejeesh Kutty
|
2e17e67627
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common/a5gt- altera 16.1 updates
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2017-06-09 16:20:15 -04:00 |
|
Rejeesh Kutty
|
688758e6c6
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scripts/adi_project_alt- add a5soc, a5gt
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2017-06-09 16:19:29 -04:00 |
|
Rejeesh Kutty
|
227bd3edfe
|
alt_ifconv-- qsys workaround
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2017-06-09 16:17:34 -04:00 |
AndreiGrozav
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033737d6bf
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adi_board.tcl: reset xilinx ip second commit
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2017-06-09 19:16:19 +03:00 |
|
AndreiGrozav
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b14c3fb00d
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Revert "adrv9371x- reset jesd ip using cpu clock"
This reverts commit 9feeb72631.
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2017-06-09 19:12:36 +03:00 |
|
Rejeesh Kutty
|
ca536d50ac
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altera 16.1 c5soc updates
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2017-06-08 15:03:03 -04:00 |
|
Rejeesh Kutty
|
f3af192f30
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altera 16.1 arradio updates
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2017-06-08 15:02:46 -04:00 |
|
Rejeesh Kutty
|
ca20309166
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adi_project_alt: add c5soc
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2017-06-08 15:02:24 -04:00 |
|
Rejeesh Kutty
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034aa7c1ee
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altera 16.1- recommends using fpll for dedicated low skew clock routing
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2017-06-08 10:50:52 -04:00 |
|
Rejeesh Kutty
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9feeb72631
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adrv9371x- reset jesd ip using cpu clock
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2017-06-08 10:49:37 -04:00 |
|
Rejeesh Kutty
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0b450a3dd7
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adi_board.tcl: reset xilinx ip using cpu clock
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2017-06-08 10:16:43 -04:00 |
Adrian Costina
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3f2c885189
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axi_logic_analyzer: Update triggering delay mechanism
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2017-06-08 12:01:49 +03:00 |
|
Adrian Costina
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256a685004
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axi_adc_trigger: Update triggering delay mechanism
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2017-06-08 12:00:27 +03:00 |
|
Rejeesh Kutty
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b8a75a7285
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hdlmake.pl - updates
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2017-06-07 10:23:20 -04:00 |
|
Rejeesh Kutty
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6100a697e8
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daq3/a10gx- alt 16.1 updates
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2017-06-07 10:23:20 -04:00 |
|
Rejeesh Kutty
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40bfd0380e
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adrv9371x/a10gx- alt 16.1 updates
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2017-06-07 09:19:14 -04:00 |
Istvan Csomortani
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83747ddb33
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ad77681evb: Fix IO constraints
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2017-06-07 14:28:39 +03:00 |
|
Istvan Csomortani
|
7554887982
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avl_dacfifo: Fix timing violation
+ Transfer avl_last_beats into dac clock domain
+ Update constraint file
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2017-06-07 11:02:44 +01:00 |
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Adrian Costina
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b7ca17f02b
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scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects
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2017-06-07 12:06:50 +03:00 |
|
Rejeesh Kutty
|
d1bab7ddb9
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hdlmake.pl- updates
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2017-06-06 16:10:05 -04:00 |
|
Rejeesh Kutty
|
3f92381bd0
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daq2/a10gx- project/constraint updates
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2017-06-06 16:09:15 -04:00 |
|
Rejeesh Kutty
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dd48929327
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hdlmake.pl - updates
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2017-06-06 12:25:35 -04:00 |
|
Rejeesh Kutty
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5176e427a1
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common/a10soc- add project create tcl procedure
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2017-06-06 12:24:13 -04:00 |
|
Rejeesh Kutty
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f278b6e6c9
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adrv9371x/a10soc- constraints/project updates
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2017-06-06 12:23:26 -04:00 |
|
Rejeesh Kutty
|
e34057c2b2
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adrv9371x/a10gx- constraints/project updates
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2017-06-06 12:22:31 -04:00 |
|
Rejeesh Kutty
|
e9c49f667f
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altera- 16.1.2 & a10soc
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2017-06-06 12:20:44 -04:00 |
|
Rejeesh Kutty
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41d305b6b6
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up_clock_mon- name changes
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2017-06-06 11:36:18 -04:00 |
|
AndreiGrozav
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4cc5052b3a
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util_fir_int: Fix valid assignment
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2017-06-06 17:53:41 +03:00 |
|
Adrian Costina
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578ccaaa44
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adrv9371x:a10gx, update create project command and Makefile
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2017-06-06 17:30:12 +03:00 |
|
Adrian Costina
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54a53c015a
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scripts: changed adi_project_create command to adi_project_altera
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2017-06-06 17:29:12 +03:00 |
|
Istvan Csomortani
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ce90769cd8
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pzsdr1: Fix IO definition for enable/en_agc
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2017-06-06 16:44:04 +03:00 |
|
Adrian Costina
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0d99aa02e1
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m2k: Updated project to work with the fifo_depth related changes
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2017-06-06 15:37:23 +03:00 |
|
Adrian Costina
|
ac55e850a9
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axi_logic_analyzer: Added trigger delay register, renamed fifo depth register
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2017-06-06 15:37:00 +03:00 |
|
Adrian Costina
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3148c85f73
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axi_adc_trigger: Added trigger delay register, renamed fifo depth register
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2017-06-06 15:35:59 +03:00 |
|
Istvan Csomortani
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491602d88b
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make: Update make files
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2017-06-06 12:00:40 +03:00 |
|
Rejeesh Kutty
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6df97a61ae
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adrv9364z7020- fix enable/en_agc mixup
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2017-06-05 16:06:27 -04:00 |
|
Rejeesh Kutty
|
eadbf9ae30
|
altera- remove default assignments from procedure
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2017-06-05 15:25:38 -04:00 |
|
Rejeesh Kutty
|
0bd22e78d9
|
altera- adi-project-create version
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2017-06-05 15:24:35 -04:00 |
|
Rejeesh Kutty
|
1b1c7ffa61
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adi_project- altera version
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2017-06-05 15:13:21 -04:00 |
|
Rejeesh Kutty
|
95c446a41d
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adi_ip- initialize xdc list when ip is created
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2017-06-01 15:49:18 -04:00 |
|
Rejeesh Kutty
|
6a437472f2
|
jesd204-sub-ip- no top files
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2017-06-01 15:48:48 -04:00 |
|
Istvan Csomortani
|
50cdb6db67
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Merge branch 'jesd204' into dev
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2017-05-31 20:44:32 +03:00 |
|
Istvan Csomortani
|
cb4e8f66ef
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axi_ad9963: Delete unused source from *_ip.tcl
|
2017-05-31 18:27:47 +03:00 |
|
Istvan Csomortani
|
84b2ad51e2
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license: Add some clarification to the header license
|
2017-05-31 18:18:56 +03:00 |
|
Istvan Csomortani
|
b6d5dbf1fc
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license: GPL must be GPL v2
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2017-05-31 18:18:45 +03:00 |
|
Adrian Costina
|
3a4a91b6f1
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util_extract: Estetic changes
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2017-05-31 11:27:32 +03:00 |
|
Rejeesh Kutty
|
2d56141bbd
|
altera- 2017-r1 16.1.2
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2017-05-30 12:21:27 -04:00 |
|
Adrian Costina
|
7aa1673238
|
util_extract: Update parameter names
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2017-05-29 16:04:56 +03:00 |