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25 Commits (dbadb9eb619fcd0426ed6a9d9af6e783f17955ff)

Author SHA1 Message Date
Robin Getz 63b6711cfa start adding some doc to the ./projects directory 
This adds a Readme.md to each project directory with pointers to project
documentation in the wiki, and the drivers (if they exist). This will
help with some autogenerated doc in the wiki, that is generated with the
innovatily named "wiki_summary.sh" shell script that parses through
these Readme.md files, and generates a summary table.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Iacob Liviu Mihai <liviu.iacob@analog.com>
 2021-11-10 14:01:06 +02:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Iacob_Liviu fec4137046 ad400xx_fmc: Parametrize board select, sampling rate and adc resolution 
fix comments
 2021-09-01 15:03:10 +03:00
Istvan Csomortani 3041e77659 ad40xx/zed: Update constraints 2021-02-04 11:04:32 +02:00
Istvan Csomortani 05469a011c ad40xx/xilinx: Activate AXI_SLICE_SRC for the DMA 2021-02-04 11:04:32 +02:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
Sergiu Arpadi da61515d41 ad40xx: Fix bd.tcl script 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Istvan Csomortani b989ba36d1 axi_spi_engine: Fix util_axis_fifo instance related issues 2021-01-08 12:29:26 +02:00
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific 
Updated all system_project and Makefiles
 2020-11-02 16:13:35 +02:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Istvan Csomortani 40772a8b2c ad40xx_fmc/zed: Fix constraints, to avoid critical warnings in synthesis 2020-09-15 13:08:39 +03:00
Istvan Csomortani 738f7af23b ad40xx_fmc: SDI delay should be set to 1 
In general we have to add a delay of half SCLK cycle.
(latch the MISO on the next consecutive SCLK edge)
 2020-08-13 10:01:16 +03:00
StancaPop 05c20af988
Merge pull request #430 from analogdevicesinc/update_tcl 
Rename projects for consistency
 2020-02-06 16:32:40 +02:00
Stanca Pop fcf7bb035a ad40xx: Fix data_width definition 2020-01-14 15:24:43 +02:00
Stanca Pop fa259c7975 ad40xx: Fix a typo 2020-01-10 10:20:06 +02:00
Stanca Pop 9497b1cace ad40xx: Remove redundant upscaler IP, Add timing constraints 2020-01-09 11:32:31 +02:00
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Sergiu Arpadi ba4a915af0 ad40xx/zed: fixed system_bd 
spi_engine_execution: fixed sdo default
 2019-06-28 11:18:29 +03:00
Istvan Csomortani cf9d0814d5 ad40xx/zed: Place all the SPI registers near IOB 2019-06-28 11:18:29 +03:00
Istvan Csomortani 10e1abc22f ad40xx_fmc/zed: Delete IOB TRUE constraints 
Vivado can not apply the IOB TRUE constraint to only one bit of a
registers. So these constraints will generate several CRITICAL WARNING.

Taking into consideration the maximum used frequencies and current
architecture these constraints are not critical.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 9ab88f1200 ad40xx: Initial commit 2019-06-28 11:18:29 +03:00