pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Istvan Csomortani	cdf01a492e	library/axi_dacfifo: Update the bypass logic The bypass logic is located between the AXI read controller and the DAC CDC fifo. When the bypass is enabled the DMAC destination interface must be clocked with the PL_DDR controller's ui_clk. This way it can easily switch between the AXI read's stream and DMAC's stream interface.	2016-06-22 12:24:54 +03:00
Istvan Csomortani	8caa783f5c	axi_dacfifo: Update the constraints	2016-05-27 14:13:55 +03:00
Istvan Csomortani	e855ef38f4	axi_dacfifo: Initial commit AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.	2016-04-19 11:28:33 +03:00

Author

SHA1

Message

Date

Istvan Csomortani

cdf01a492e

library/axi_dacfifo: Update the bypass logic

The bypass logic is located between the AXI read controller and the
DAC CDC fifo. When the bypass is enabled the DMAC destination interface
must be clocked with the PL_DDR controller's ui_clk. This way it can easily
switch between the AXI read's stream and DMAC's stream interface.

2016-06-22 12:24:54 +03:00

Istvan Csomortani

8caa783f5c

axi_dacfifo: Update the constraints

2016-05-27 14:13:55 +03:00

Istvan Csomortani

e855ef38f4

axi_dacfifo: Initial commit

AXI DAC fifo, which use the PL side DDR memory. The minimum data granularity is 1kbyte.

2016-04-19 11:28:33 +03:00

3 Commits (db6d5f509f92e9610ccf626dbfa00cb259606005)