fe8a076b2e
fmcomms2: Cosmetic changes on *_bd.tcl script
2014-10-10 17:06:32 +03:00
7a9e694446
fmcomms2: Connect DMA directly to the HP ports
...
The DMA controller is able to send AXI3 compatible requests, no need to add
a interconnect for protocol conversion in between the DMA controller and the
HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:14 +03:00
87047fd83e
fmcomms2: Set dac_unpack channels to 4
...
There are only 4 DAC channels in the fmcomms2 design, so set the number of
channels of the dac_unpack core to 4. This slightly reduces resource usage
as well as reducing the DMA alignment requirement from 128bit to 64bit. The
later value is what existing applications expect the alignement requirement
to be.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:06 +03:00
2da395926e
fmcomms2: Upgrade project to 2014.2
2014-10-09 18:54:33 +03:00
7e40f99fe9
fmcomms2: Improved constraints for ac701 and zc702. Fixed common design so that ILA works correctly on microblaze based systems
2014-09-23 22:28:27 -04:00
f43b5d707e
fmcomms2: Reduced clock frequency for ILA to meet timing for ZED
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Modified ZED constraints to 250 MHz for the clock from AD9361
2014-09-16 16:08:28 -04:00
95c143412d
fmcomms2: Modified design to work with 4 channel util_adc_pack
2014-08-29 13:53:59 +03:00
7000897031
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
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The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
ba7955c531
fmcomms2: register map modifications
2014-06-26 10:09:03 -04:00
bef6a9c32c
axi_ad9361: Split dma data into individual channels for both ADC and DAC
2014-06-07 17:15:31 +03:00
1d53d79e25
fmcomms2/common: Fix ad9361's interface
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Loopback the l_clk to clk. l_clk is the device sampling clock, clk is used to
synchronize the cores in case of a multiple device configuration.
2014-05-21 10:09:54 +03:00
25e4520726
fmcomms2/common: Delet trailing white spaces
2014-05-21 09:47:37 +03:00
5aac9d7288
FMCOMMS2 added sync option
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Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
814b0d72d6
Modified Reset signals for FMCOMMS2 base design
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Made all resets the same (sys_100m_resetn)
2014-04-01 15:32:48 +03:00
31a1ff384d
FMCOMMS2 Base Design tcl modified
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Added support for both Zynq and MicroBlaze projects
2014-03-21 09:57:52 +02:00
2c898bf3a2
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project
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ZC706 runs rx_clk at 250 MHz.
ZC702 and ZED run rx_clk at 200 MHz due to slower fabric.
The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly.
Both DDS and DMA mode work.
2014-03-18 15:27:42 +02:00
ee56db8d50
FMCOMMS2: Modified FCLK2 to 125 MHz, and xdc file
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tcl: FCLK2 was modified from 100 MHz to 125 MHz.
xdc: rx_clk period constraint was redefined from 8ns (125 MHz) to 4ns (250 MHz)
2014-03-14 16:27:56 +02:00
a6c3cb29c6
Modified SPI and ILA in fmcomms2_bd.tcl
2014-03-12 16:52:22 +02:00
66c6b2b182
fmcomms2: added
2014-03-11 20:04:26 -04:00
Istvan Csomortani
Lars-Peter Clausen
Adrian Costina
Rejeesh Kutty
ATofan