b989ba36d1
axi_spi_engine: Fix util_axis_fifo instance related issues
2021-01-08 12:29:26 +02:00
9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
40772a8b2c
ad40xx_fmc/zed: Fix constraints, to avoid critical warnings in synthesis
2020-09-15 13:08:39 +03:00
738f7af23b
ad40xx_fmc: SDI delay should be set to 1
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In general we have to add a delay of half SCLK cycle.
(latch the MISO on the next consecutive SCLK edge)
2020-08-13 10:01:16 +03:00
05c20af988
Merge pull request #430 from analogdevicesinc/update_tcl
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Rename projects for consistency
2020-02-06 16:32:40 +02:00
fcf7bb035a
ad40xx: Fix data_width definition
2020-01-14 15:24:43 +02:00
fa259c7975
ad40xx: Fix a typo
2020-01-10 10:20:06 +02:00
9497b1cace
ad40xx: Remove redundant upscaler IP, Add timing constraints
2020-01-09 11:32:31 +02:00
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
ba4a915af0
ad40xx/zed: fixed system_bd
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spi_engine_execution: fixed sdo default
2019-06-28 11:18:29 +03:00
cf9d0814d5
ad40xx/zed: Place all the SPI registers near IOB
2019-06-28 11:18:29 +03:00
10e1abc22f
ad40xx_fmc/zed: Delete IOB TRUE constraints
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Vivado can not apply the IOB TRUE constraint to only one bit of a
registers. So these constraints will generate several CRITICAL WARNING.
Taking into consideration the maximum used frequencies and current
architecture these constraints are not critical.
2019-06-28 11:18:29 +03:00
9ab88f1200
ad40xx: Initial commit
2019-06-28 11:18:29 +03:00
Istvan Csomortani
Adrian Costina
Sergiu Arpadi
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