d949936a1b
adrv9009zu11eg/common: EXT_SYNC updates
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- Explicitly enable EXT_SYNC parameter for Rx/Obs
- Loopback manual sync for each TPL (we do not combine them yet because
it requires extra CDC logic)
2022-02-07 19:14:01 +02:00
f245448976
ad_ip_jesd204_tpl_ : Add missing dependency
2022-02-07 19:14:01 +02:00
b5092662d5
ad_ip_jesd204_tpl_adc: Refactor external sync
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- Add EXT_SYNC option
- Gate valid while in reset
2022-02-07 19:14:01 +02:00
8c7cca4277
common/up_adc_common: Add ext sync regs
2022-02-07 19:14:01 +02:00
1b06c74919
common/up_dac_common: Add manual sync request
2022-02-07 19:14:01 +02:00
db49aa652f
common/up_dac_common: Add support for explicit disarm control
2022-02-07 19:14:01 +02:00
4e644e4e74
jesd204/ad_ip_jesd204_tpl_dac: External sync refactor
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- Expose EXT_SYNC parameter to sw
- Add external manual sync request
- Add rst to interface
2022-02-07 19:14:01 +02:00
1ca5abc91e
common/up_xfer_cntrl: Fix transfer done timing
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up_xfer_done should signalize when a previous control set is
transferred to the other clock domain and the current control set is latched.
If a bit from the up_data_cntrl changes, it should stay in that state until
the up_xfer_done asserts.
2022-02-07 19:14:01 +02:00
63a1233101
ad7134_fmc: Update Readme
2022-02-07 14:41:25 +02:00
4827e5eb18
ad7134_fmc: Switch offload trigger to falling ODR
2022-02-07 14:41:25 +02:00
297bed6721
ad7134_fmc: Change ODR signal to output
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FPGA is now generating the ODR signal using axi_pwm_gen.
Both ADCs are now in slave mode.
2022-02-07 14:41:25 +02:00
b63ebca292
projects/cn0506_rmii/*: Add util_mii_to_rmii library to project
2022-02-03 10:23:12 +02:00
170ce42e3e
util_mii_to_rmii: Initial commit
2022-02-03 10:23:12 +02:00
3da9d9fcb4
pluto_ng: Initial commit
2022-02-03 09:56:13 +02:00
7dae0858b0
de10nano: changed quartus version to 20.1.1
2022-01-31 14:10:51 +02:00
38f3627695
ad_dds: Fix DDS start samples
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When using a CLK_RATIO > 1 the first n samples(n=CLK_RATIO) after sync, are
noisy. This is because the phase accumulator data is passed to the phase to
amplitude converter, during the phase synchronization step.
2022-01-31 14:07:11 +02:00
bc5974d789
ad77681evb: Fix irq overlap
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spi engine irq signal was overwriting fmc iic irq
2022-01-31 12:32:31 +02:00
f34b561e19
daq3: Parameterize JESD204 configuration values
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Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-31 10:47:01 +02:00
e8ff32d6df
ad6676evb: Parameterize JESD204 configuration values
...
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-31 10:36:31 +02:00
318523579f
ad6676evb: Update to JESD204 TPL instantiation
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Updated the JESD204 TPL instantation of the design.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-31 10:36:31 +02:00
b26b4c00f0
ad9783: Clean-up parameters and module instances
2022-01-25 18:24:43 +02:00
9ca5ae07b2
ad9783: Add Readme.md
2022-01-25 17:16:30 +02:00
889447e900
axi_ad9361: make IODELAYCTRL insertion optional
2022-01-25 09:50:31 +02:00
bc8e7881f2
axi_dmac: Hook up ID
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Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2022-01-25 09:50:22 +02:00
530aca9754
daq2: Parameterize JESD204 configuration values
...
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line for the Xilinx FPGAs in the project.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-20 12:54:03 +02:00
f3cf7508c8
ad9783: Update Makefile
2022-01-20 12:31:57 +02:00
4ec8797c7c
adrv9009: Parameterize JESD204 configuration values
2022-01-13 10:15:05 +02:00
9d94f21d89
scripts/adi_xilinx_device_info_enc.tcl: Change regex for vcu128
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The regex does not match vcu128 as Ultrascale+. It matches for Ultrascale.
2022-01-12 17:32:47 +02:00
6a92bd5925
adrv9371x: Parameterize JESD204 configuration values
2022-01-12 16:05:48 +02:00
d8a418d8d0
projects/scripts/adi_board/tcl: Updated ad_xcvrcon procedure for parametrized projects
2022-01-12 16:05:18 +02:00
9d8097389c
library/jesd204/jesd204_common/pipeline_stage.v: Initialize pipeline stage register
2022-01-12 13:43:20 +02:00
fc04198b2b
adrc9361_ccfmc: Fix SFP pin locations
2022-01-12 13:43:06 +02:00
86d2467f57
fmcjesdadc1: Parameterize JESD204 configuration values
...
Added the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2022-01-12 13:28:42 +02:00
080925e8fe
library/jesd204: tpl timing bug fix
2022-01-12 10:14:55 +02:00
3d000ee6a8
ad9783_zcu102_dev: Initial commit
2022-01-07 14:04:08 +02:00
08f029c757
axi_ad9783: Initial commit
2022-01-07 14:04:08 +02:00
fcd3bfd349
util_pulse_gen: Reload registers when counter is at one
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This patch fixes an issue where the pulse width is only updated two
periods after the current one.
Signed-off-by: David Winter <david.winter@analog.com>
2022-01-04 15:02:05 +02:00
6dddaaaa78
adrv9009zu11eg/adrv2crr_xmicrowave: Update Makefile
2021-12-22 11:33:15 +02:00
0d45f4dc94
xmicrowave: Fix typo
2021-12-17 15:44:23 +02:00
c2d960e029
axi_adrv9001: Add external sync support
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The external sync must be synchronous to the reference clock, in order
to obtain a deterministic synchronization of the interface.
2021-12-16 15:16:30 +02:00
38c489d254
projects: set Quartus version for cyclone5, cn0506_mii and cn0506_rgmii
2021-12-15 17:13:38 +02:00
fb17147eb4
fmcadc2: Parameterize JESD204 configuration values
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Add the capability to set the JESD204 configuration values from a single
point in the code and to modify these default settings from the command
line.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-10 20:54:39 +02:00
13a282d9c4
fmcadc2: Update JESD204 TPL instance
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Updated the JESD204B transport layer instance to instantiate the new TPL IP
module.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-10 20:54:39 +02:00
41525f348b
axi_adrv9001/axi_adrv9001_core.v: Disable TDD and IOCTRL if second SSI interface is disabled
2021-12-08 17:31:53 +02:00
dfe153dc68
axi_adrv9001/axi_adrv9001_tdd.v: Add disable option for TDD
2021-12-08 17:31:53 +02:00
8cc0367e8f
axi_adrv9001: Hide disabled interfaces
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Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-12-08 17:31:53 +02:00
6a4b46ebb4
axi_adrv9001: Make Rx2 and Tx2 source synchronous interfaces optional
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If the Rx2 and Tx2 SSI are disabled the rx1,tx2 data paths are forced to
R1 mode.
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-12-08 17:31:53 +02:00
77f3e5155b
ad9081_fmca_ebz: Fix signal length parameter
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Corrected the length parameter for the rx_data input.
Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>
2021-12-08 14:29:48 +02:00
040d5732c7
README.md: Add link to boot partition files download link
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Add in README.md how to use and from where to get already built boot files.
Signed-off-by: stefan.raus <stefan.raus@analog.com>
2021-12-07 14:42:42 +02:00
1b8ca5f045
fmcjesdadc1: bd: Clean trailing white spaces and alignment
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Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2021-12-03 16:10:51 +02:00
Laszlo Nagy
sergiu arpadi
alin724
AndreiGrozav
Iacob_Liviu
Dan Hotoleanu
Iulia Moldovan
Filip Gherman
David Winter
Stanca Pop
stefan.raus