2e173201d4
daq2: daq2_qsys.tcl: Use sys_dma_clk
...
Use the sys_dma_clk clock module for clock and reset signals of the data
path, rather than using the A10GX specific sys_ddr3_cntrl signals. This
enables compatibility for all Altera/Intel platforms.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-17 17:38:20 +02:00
0360e8587e
Connect JESD204 interrupts
...
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
2e8be3d7a6
daq2: Provide DAC lane map
...
Provide the correct lane mapping for the DAQ2 DAC lanes which do not follow
a 1-to-1 mapping between physical and logical lanes due to PCB layout
constraints.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-06-20 17:39:41 +02:00
50cdb6db67
Merge branch 'jesd204' into dev
2017-05-31 20:44:32 +03:00
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
85ebd3ca01
license: Update license terms in hdl source files
...
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
0ec92d3153
daq2: Convert to ADI JESD204
...
Convert the DAQ2 project to the ADI JESD204 link layer cores. The change is
very straight forward, but a matching change on the software side is
required.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
9055774795
all: Update license for all hdl source files
...
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.
New license looks as follows:
Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.
Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
(at the option of the user):
1. The GNU General Public License version 2 as published by the
Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
OR
2. An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
ebeebdddf0
altera- infer latest versions
2017-05-12 13:40:14 -04:00
1c23cf4621
all: Update verilog files to verilog-2001
2017-04-13 11:59:55 +03:00
454e6c0382
daq2- ad-ip-instance & ad-ip-parameter
2017-04-06 13:04:53 -04:00
191669ad28
daq2_common: Fix the dac_rst for DAC FIFO
2017-03-07 16:13:46 +02:00
4a6fe54fcf
daq2_common: Update common scripts
...
Add new port connection for util_dacfifo
2017-03-03 18:49:10 +02:00
6b1a8852a9
dacfifo- bypass port name change
2017-02-27 16:06:39 -05:00
daa3df4b96
projects/- xcvr updates
2016-11-22 16:23:05 -05:00
b1a9bd96f1
daq2: xcvr pll changes
2016-11-22 12:53:29 -05:00
cac4057449
daq2/common: Altera updates
2016-11-15 16:03:52 +02:00
3b55822db3
daq2- xcvr connect
2016-10-06 14:09:27 -04:00
236a938425
daq2/a10gx- qsys updates
2016-09-12 14:57:50 -04:00
ed9e92621c
daq2- spi+xcvr address conflict
2016-08-04 10:50:31 -04:00
9a563de8ff
daq2: A10GX updated project to Quartus 16.0
...
- connected directly axi_ad9680 to xcvr_core, skipping axi_jesd_xcvr
2016-08-01 15:09:53 +03:00
9952a94efb
hdl-vivado-2016.2- ip version updates
2016-07-28 13:44:57 -04:00
6df5ba1a7a
daq2- adxcvr version
2016-07-21 16:09:33 -04:00
625052f46e
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
3516ec28b7
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
39d23032f1
daq2- qsys updates
2016-05-23 10:55:44 -04:00
e00236e5fd
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:04:46 -04:00
679d471d75
Merge branch 'hdl_2016_r1' into dev
...
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
2016-04-19 18:05:50 +03:00
1fab6ce477
daq2/common: Add util_dacfifo/dac_xfer_out control
2016-03-29 16:55:33 +03:00
657144d9a7
a10gx: Updated base design and DAQ2 to the new revision of the a10gx board
...
- tried using ATX PLL and fPLL for TX transceiver clocks, but could not get them to lock
- CMU PLL works correctly as temporary solution
2016-03-28 13:21:36 +03:00
b7be089b82
daq2: Updated common design to 2015.4
2016-03-16 10:02:42 +02:00
40fb68dfd5
ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible
2016-03-02 13:39:37 +02:00
becc23a69b
daq2: Modified common spi module so that spi streaming is possible
...
- stop incrementing spi_count after the instruction cycle
2016-03-01 17:25:58 +02:00
8ccd8d87bb
daq2: A10GX, increase analog/digital reset durations
...
- reset the xcvr_rst_cntrl only from the axi_jesd_xcvr
- checked separate RX/TX reset per channel
2016-02-23 11:41:38 +02:00
ad9ecbbbb6
daq2: Updated a10gx project to quartus 15.1.1
2016-02-05 17:43:05 +02:00
a81625e1fa
daq2: Updated a10gx project
2015-11-24 13:28:53 +02:00
e36f27b061
daq2: Update A10GX project, with the latest changes.
...
Works with up to 64k samples
2015-11-04 14:54:09 +02:00
7184827d68
daq2: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:54 +02:00
58fa29b673
daq2- jesd core upgrade
2015-08-27 11:18:00 -04:00
2dabf98089
parameter changes
2015-08-20 08:54:13 -04:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
...
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
0ec17fd4d6
daq2-a10gx- parameter changes
2015-08-19 14:56:00 -04:00
f40abf171f
cpack- adc_rst added
2015-08-19 13:26:38 -04:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
c72cf99562
daq2- gt changes
2015-08-17 14:11:58 -04:00
b4eac232db
a10gx- move cores inside qsys
2015-07-21 11:06:45 -04:00
445c4c835d
daq2-bd: xcvr components
2015-07-21 10:54:23 -04:00
2f53dc4412
daq2- board system only
2015-07-20 09:30:32 -04:00
a2e7fb9491
daq2/a10gx: qsys signal tap version
2015-07-13 10:07:18 -04:00
825fddd034
transceiver split up outside qsys
2015-07-10 11:45:07 -04:00
Lars-Peter Clausen
Istvan Csomortani
Rejeesh Kutty
AndreiGrozav
Adrian Costina
Shrutika Redkar