Commit Graph

17 Commits (d4820dd55a87d63bb8ea11f39d375e4f676623f9)

Author SHA1 Message Date
Lars-Peter Clausen 374c49ff48 axi_dmac: axi_dmac_hw.tcl: Automatically detect clock domains
Qsys allows to query to query the clock domain that is associated with a
clock input of a peripheral. This allows to automatically detect whether
the different clocks of the DMAC are asynchronous and CDC logic needs to be
inserted or not.

Auto-detection has the advantages that the configuration parameters don't
need to be set manually and the optional configuration will be choose
automatically. There is also less chance of error of leaving the settings
in a wrong configuration when e.g. the clock domains change.

In case the auto-detection should ever fail configuration options that
provide a manual overwrite are added as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-24 16:06:37 +02:00
Istvan Csomortani 1541943ff2 adrv9371_alt: Delete the fifos from the RX path
+ Delete the rx_fifo and rx_os_fifo from the RX datapath
  + Change the receive DMA's source interface type to wr_fifo
2017-06-22 11:58:10 +01:00
Rejeesh Kutty 4f0accbbfa adrv9371x fix dacfifo name 2017-05-18 12:54:14 -04:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Istvan Csomortani 6ed721ee66 adrv9371/a10soc: Integrate the avl_dacfifo into project 2017-04-21 13:27:35 +03:00
Rejeesh Kutty 8f1564a9c4 adrv9371x/a10gx- gpio matching 2017-03-27 13:51:45 -04:00
Rejeesh Kutty 762276a880 adrv9371x- dacfifo changes 2017-03-06 10:33:52 -05:00
Rejeesh Kutty bc6a09c828 adrv9371x/a10soc- dacfifo added 2017-03-01 15:35:04 -05:00
Rejeesh Kutty 2d7fb03b93 adrv9371x/a10gx- fix os xcvr parameters 2016-12-06 12:31:40 -05:00
Rejeesh Kutty f752f0c9d7 a10soc- xcvr updates 2016-10-27 09:25:00 -04:00
Adrian Costina e40311eee9 adrv9371x: A10soc, connected DMAs through 128 bit SDRAM0 port at 175MHz 2016-09-29 09:14:37 +01:00
Adrian Costina f5809b8817 adrv9371x: a10soc, added adcfifos; connected the new reset to all peripherals; used the new f2sdram1 port 2016-09-24 10:09:05 +03:00
Adrian Costina 521c41ce32 adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier 2016-09-08 11:44:45 +03:00
Adrian Costina d18f6aa816 adrv9371x: A10GX, added adcfifo
- connected dac dma to 133 MHz clock
- set explicit clock rate to xcvr reference clock bridge
2016-08-26 14:46:48 +03:00
Adrian Costina 215edb11c6 adrv9371: A10GX, updated design
- disable reconfiguration for RX transceivers and enabled the reconfiguration for TX transceiver. They cannot be enabled at the same time at this point
- update FIFO SIZE to 16 for all DMAs
- updated memory connections to 256 bit and moved clock connection to 133 MHz, for all DMAs.
2016-08-23 18:25:48 +03:00
Adrian Costina 41203d07e9 adrv9371x: A10GX, update SPI connection 2016-08-18 17:42:27 +03:00
Adrian Costina 5c27ccd1fa adrv9371x: Added common qsys tcl 2016-08-16 15:34:10 +03:00