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6 Commits (d47776a4a0984cfb6ae7ef45bdeff498b8606206)

Author SHA1 Message Date
Lars-Peter Clausen de0edc2083 axi_dmac: src_fifo_inf: Clear pipeline when no transfers are active 
Clear the pipeline when no transfers are active to make sure that we do not
get residual data on the first sample for the next transfer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-16 21:02:05 +02:00
Lars-Peter Clausen 8a2b29cdbe axi_damc: Add xfer_req to the FIFO source interface 
The xfer_req signal will be high if DMA core the is expecting data.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-07-02 16:05:16 +02:00
Lars-Peter Clausen cb630e36a9 axi_dmac: src_fifo_inf: Simplify data path 
Improves timing a bit

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-04-10 13:50:39 +02:00
Lars-Peter Clausen e373b85954 axi_dmac: Fix Vivado warnings 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-18 20:59:13 +01:00
Lars-Peter Clausen f02ba999ae axi_dmac: Add support for DMA bus widths other than 64 bit 
There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-13 13:20:10 +01:00
Adrian Costina 831c19ea84 Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00