Commit Graph

89 Commits (d471b61f3ee47b194868292c5cb3e1eb74ad7859)

Author SHA1 Message Date
Rejeesh Kutty d471b61f3e fifo: merge zynq and non-zynq 2014-10-27 09:59:54 -04:00
Istvan Csomortani 10b898a62d zed_base: Fix IRQ layout.
Just a temporally fix of IRQ layout.
2014-10-27 14:46:26 +02:00
Rejeesh Kutty 43cdafe1e2 kcu105: iic-rstn removed 2014-10-22 16:33:52 -04:00
Istvan Csomortani dcdba475f7 vc707_common: Fix net name sys_100m_resetn 2014-10-22 15:41:36 +03:00
Istvan Csomortani 767179dce9 adv7511_zc706: Fix IRQ layout
Fix IRQ connection, this layout works on Linux
2014-10-21 17:44:28 +03:00
Istvan Csomortani 5deffd57b1 zed: Remove top level constraints
Remove top level constraints from the ZED base design.
2014-10-20 13:20:27 +03:00
Rejeesh Kutty 14ccdaaa78 kcu105: removed spdif reset 2014-10-17 14:00:00 -04:00
Rejeesh Kutty e73b3b52dc kcu105: ethernet fix 2014-10-17 13:47:50 -04:00
Rejeesh Kutty 6d76e0b768 zc706: remove top level constraints 2014-10-15 14:51:02 -04:00
Rejeesh Kutty 5715c5b28f dmafifo: axi stream interface 2014-10-15 14:50:57 -04:00
Lars-Peter Clausen 7d3be14ab5 common: Connect audio clkgen reset
While we are at it also hide the unused locked pin.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:44:46 +03:00
Lars-Peter Clausen fd89458708 common: Set cpu interconnect strategy to minimize area
There will rarely be concurrent access to the peripheral control bus
interconnect, so there is no need to optimize for performace. Setting the
interconnect strategy to minimize area can reduce the resource usage by
~90%.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:43:54 +03:00
Istvan Csomortani d2a04856a9 common: Fix xlconstant output pin name
On 2014.2 xlconstant output pin name is 'dout'.
2014-10-15 15:37:06 +03:00
Lars-Peter Clausen 43e9b0c7a6 common: Disable TTC0 MMIO routing for PS7
We do not use the ttc0 to MMIO routing, but it is enabled by default, so
explicitly disable it.
2014-10-10 16:19:51 +03:00
Istvan Csomortani 4f6aa159b8 mitx045: Base design now support 2014.2 2014-10-09 15:11:28 +03:00
Michael Hennerich cd42345324 projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-07 09:17:24 +02:00
Rejeesh Kutty f0927afd0b ad9625_fmc: add dma fifo for non-zynq 2014-10-01 14:51:14 -04:00
Adrian Costina 041d8faaf7 common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2 2014-09-30 10:31:00 +03:00
Rejeesh Kutty 7c98a783c5 2014.2 updates 2014-09-23 12:32:33 -04:00
Istvan Csomortani dd7bac41c1 daq1 : Update project to 2014.2
- Cores are upadted
  - Concat module does not swap output anymore
  - Clock signal name ps7_clk_* changed to clk_fpga_*
2014-09-22 17:33:50 +03:00
Rejeesh Kutty fb5d212370 daq2/kcu105: fixed timing violations 2014-09-19 15:55:42 -04:00
Michael Hennerich a3dbd5ac00 projects/common/vc707/vc707_system_bd: AD9625_FMC update to 2014.2
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-09-16 14:59:36 +02:00
Lars-Peter Clausen 41cc92ef49 Remove BASEADDR/HIGHADDR parameters
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
Michael Hennerich 647a26e19c projects/common/vc707/vc707_system_bd.tcl: Select Linux MMU settings 2014-09-10 17:40:36 +02:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
Rejeesh Kutty b58e425b44 daq2/kcu105: timing improvement -register slices hang 2014-09-08 10:24:56 -04:00
Rejeesh Kutty 72f31370ef a5gt: ethernet-fpga lvds mode 2014-09-04 11:19:25 -04:00
Rejeesh Kutty 3deb55bb98 a5gt: ethernet i/o changed to lvds 2014-09-04 11:19:24 -04:00
dbogdan 5a42c10233 projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI. 2014-08-27 21:46:23 +03:00
Rejeesh Kutty 7b280b3bbf fmcomms6: zc706 build-only version 2014-08-27 10:44:37 -04:00
Adrian Costina a49eb5853b ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems
For ZC706 Fixed one constraint which was not correct
2014-08-26 16:28:41 +03:00
Rejeesh Kutty cb29b83b05 a5gt: updates to match a5gt 2014-08-25 10:46:59 -04:00
Rejeesh Kutty b481df0b5f library: local constraints async groups 2014-08-14 15:09:51 -04:00
Rejeesh Kutty 39bb7ca231 a5soc: fmcjesdadc1+hdmi version 2014-08-14 09:05:38 -04:00
Rejeesh Kutty 96969079ce a5soc: fixes for 14.0 and spi conflicts 2014-08-11 16:46:37 -04:00
Adrian Costina 6c6cab0e16 fmcomms2: ZC706 modified constraints for linux build machines
The added constraints allow the project to successfully pass timing on some ubuntu or debian build machines.
2014-08-01 17:34:36 +03:00
Rejeesh Kutty 663588eeaf daq2/kcu105: working ddr version 2014-07-29 09:15:30 -04:00
Rejeesh Kutty db2386a351 daq2/kcu105: latest mig updates 2014-07-23 16:25:55 -04:00
Istvan Csomortani db1c931736 ad9625_plddr: PL DDR3 fixes
- Modified the axi slave interface handler
  - Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
Istvan Csomortani 2b6ce1e504 zc706_plddr3 : Fix axi_fifo2s_axi_mrst net 2014-07-21 15:10:36 +03:00
Rejeesh Kutty 2955b9db78 fifo2s: flush if no request, c5soc: 14.0 2014-07-15 16:25:33 -04:00
Rejeesh Kutty b434fe6dd5 fmcomms5: register map changes 2014-07-08 16:57:43 -04:00
Rejeesh Kutty c75e6b3043 kcu105 pwr-good removed 2014-07-07 09:56:13 -04:00
Rejeesh Kutty a388ccab0a fmcomms2/c5soc: initial checkin 2014-07-02 14:56:00 -04:00
Rejeesh Kutty c1b7fc17f5 c5soc: initial a5soc copy 2014-07-01 13:05:26 -04:00
Rejeesh Kutty e38813fa9f fifo- monitor status signals 2014-06-25 12:15:13 -04:00
Rejeesh Kutty 57bb3705f2 zc706-plddr3: read changes to lower dma clock 2014-06-25 09:20:58 -04:00
Rejeesh Kutty 6ea7dd7fc3 kcu105: pwr-good added 2014-06-12 15:22:31 -04:00
Adrian Costina 2837d788a6 mitx045: Added I2S core to the base design 2014-06-06 17:53:47 +03:00
Rejeesh Kutty cf56a568c6 kcu105: GTH updates 2014-06-05 14:27:38 -04:00