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1970 Commits (d2e7b6b635f95e4fa91908f5b6f370c4480c8bcc)

Author SHA1 Message Date
Adrian Costina d2e7b6b635 fmcomms5: Added FIFOs for DAC and ADC paths so that they work at l_clk/2 or l_clk/4 2017-01-13 14:18:59 +02:00
Adrian Costina a36057679a fmcomms2: Update Makefiles 2017-01-13 14:16:21 +02:00
Adrian Costina 15c5bc7012 fmcomms2: zcu102, changed clkdiv C_SIM_DEVICE parameter to ultrascale 2017-01-13 13:57:32 +02:00
Adrian Costina b84325d43f fmcomms2: take into consideration both adc_r1 and dac_r1 for clock division selection 2017-01-13 13:56:04 +02:00
Adrian Costina e77428c50e fmcomms2: Added FIFOs for DAC and ADC paths so that the path works at l_clk / 2 or l_clk /4 
- removed ILA
 2017-01-11 18:12:35 +02:00
Rejeesh Kutty 37d54bb984 fmcjesdadc1/a5gt- max delay fit only 2017-01-04 16:04:19 -05:00
Rejeesh Kutty 8b74e911b8 fmcjesdadc1/a5gt- qr to ddio max delay 2017-01-04 14:10:44 -05:00
Istvan Csomortani e4e5b30ade fmcadc5: Integrate ad_sysref_gen into the project 2017-01-03 13:52:39 +02:00
Rejeesh Kutty 14ded4f123 fmcjeadadc1/a5soc- ad_sysref_gen updates 2016-12-22 15:59:45 -05:00
Rejeesh Kutty b089173b4c fmcjesdadc1/a5soc- cpu clock is 50m for a5gt also 2016-12-22 14:14:21 -05:00
Rejeesh Kutty aa6c94c993 usdrx1/a5gt: ddr3 use ip constraints 2016-12-22 14:14:21 -05:00
Rejeesh Kutty 18660c7ab4 fmcjesdadc1/a5gt: ddr3 use ip constraints 2016-12-22 14:14:21 -05:00
Rejeesh Kutty 2bea337aa2 fmcjesdadc1/a5gt- use 50m-mem-cpu-clk 2016-12-22 14:14:21 -05:00
Rejeesh Kutty 5d683943ab fmcjesdadc1/a5gt- remove ad-sysref-gen-pack 2016-12-22 14:14:21 -05:00
Rejeesh Kutty f1168f9e29 fmcjesdadc1/a5gt- use xilinx setup 2-dma 2016-12-22 14:14:21 -05:00
Rejeesh Kutty 1ceec2e2a9 projects/a5gt- use 50m afi clock for cpu- xcvr reconfig timing 2016-12-22 14:14:21 -05:00
Rejeesh Kutty eba30b0cde projects/altera- qii_auto_pack option 2016-12-22 14:14:21 -05:00
Rejeesh Kutty 4a783d523d projects/altera* - default & common qsys commands 2016-12-20 16:27:44 -05:00
Rejeesh Kutty 3e57ff1fc5 z-mpsoc- map 0x4-0x8,0x7-0x9 2016-12-20 16:14:38 -05:00
Istvan Csomortani 1156aeac16 ad_sysref_gen: Update SYSREF related constraints 2016-12-19 18:07:05 +02:00
Istvan Csomortani da7f4608a8 fmcjesdadc1/usdrx1: Clean up the mess 
Delete accidentally commited generated files.
 2016-12-19 15:35:20 +00:00
Istvan Csomortani f47863bbcf usdrx1: Integrate ad_syref_gen into the project 2016-12-19 14:36:01 +00:00
Istvan Csomortani 8d799d0316 fmcjesdadc1: Intergrate ad_sysref_gen into project 2016-12-19 13:37:29 +00:00
Istvan Csomortani 0c42e04bc3 fmcadc2: Integrate ad_sysref_gen into the project 2016-12-19 12:16:05 +00:00
Istvan Csomortani 67390c2a95 ad6676evb: Update projects with ad_sysref_gen 2016-12-19 10:52:25 +00:00
Adrian Costina 8879218502 a5gte: Fixed timing violations 2016-12-16 15:37:51 +02:00
Istvan Csomortani c0b0f9b7e9 ad6676evb: Connect SYS_REF to GPIO 2016-12-14 17:55:50 +02:00
Istvan Csomortani 557efed5d9 ad6676evb: Update clock constraints 2016-12-14 17:55:49 +02:00
Istvan Csomortani 3a2c889115 ad6676evb: Update GT configuration 2016-12-14 17:55:49 +02:00
AndreiGrozav d962614000 usdrx1/zc706: Disabele axi_spi constraint file 
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
 2016-12-13 19:23:51 +02:00
AndreiGrozav d5165ca81f motcon_fmc: Tie unused pins to GND 2016-12-13 19:20:13 +02:00
AndreiGrozav 1515b6f1af fmcomms7/zc706: Disabele axi_spi constraint file 
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
 2016-12-13 19:18:18 +02:00
AndreiGrozav 8846141467 fmcomms1/kc705: Disabele axi_spi constraint file 
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
 2016-12-13 19:16:31 +02:00
AndreiGrozav c455d2d64f fmcadc2/vc707: Disabele axi_spi constraint file 
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
 2016-12-13 19:15:44 +02:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
Istvan 06aab8ebbd pzsdr1: Set the device core to 1R1T mode 2016-12-09 16:35:46 +02:00
AndreiGrozav 8e69c838e1 common/ac701: Connect axi_ddr_cntrl/device_temp_i to GND 2016-12-09 13:54:39 +02:00
Istvan 23c91ca48a pzsdr1/lvds: The interface runs at max 122.88 MHz 2016-12-09 11:45:11 +02:00
Rejeesh Kutty f799c40cf0 usdrx1/a5gt- xcvr interface changes 2016-12-08 16:05:23 -05:00
Rejeesh Kutty c114888956 usdrx1- updates 2016-12-08 16:05:23 -05:00
AndreiGrozav b0eff57b0f fmcomms2/zc702: Fix critical warnings 2016-12-08 19:54:52 +02:00
AndreiGrozav 3dceb53984 fmcadc2/vc707: Fix timing violations 2016-12-08 19:51:18 +02:00
Istvan 252c67ceff fmcomms6: Delete project 
This project will not be supported in further releases.
 2016-12-08 17:22:41 +02:00
Rejeesh Kutty fb287d0178 kcu105- updates to match xilinx trd 2016-12-08 09:32:33 -05:00
AndreiGrozav 3bc9df4c51 fmcomms5: Fixed the wornings created by TDD missing connections to axi_ad9361 core 2016-12-07 21:43:19 +02:00
AndreiGrozav 8eaae98728 fmcadc2: Updates 2016-12-07 21:43:19 +02:00
Rejeesh Kutty 801da3cb25 daq3/kcu105- fix timing violations 2016-12-06 12:31:40 -05:00
Rejeesh Kutty 2d7fb03b93 adrv9371x/a10gx- fix os xcvr parameters 2016-12-06 12:31:40 -05:00
Istvan Csomortani ad96c5e881 daq3/zc706: Change the speed grade of the FPGA to 3 2016-12-06 15:24:23 +02:00
Istvan Csomortani 8f94103f8b daq1/a10gx: Makefile fix 2016-12-06 15:24:23 +02:00