Lars-Peter Clausen
cfc51016ea
pzsdr1/pzsdr2: audio_clkgen: Infer input clock frequency
...
Instead of manually specifying the input clock frequency let the core infer
it automatically. This makes it more straight forward to change the clock
frequency.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-04-21 13:22:19 +02:00
Rejeesh Kutty
ddfbdfd2f7
pzsdr1/pzsdr2- ccbox added tws
2017-04-18 11:37:23 -04:00
Adrian Costina
86c279c238
pzsdr1: ccbox, moved I2S core to DMA0 and DMA1 to fix critical warnings
2017-02-14 14:51:49 +02:00
Adrian Costina
acef0113d1
pzsdr1: ccusb, connect unused clock pins to GND
2017-02-14 11:50:37 +02:00
Adrian Costina
46883731eb
pzsdr1: Don't set a disabled parameter
2017-02-14 11:50:06 +02:00
Adrian Costina
165ba76d9d
pzsdr1: Added FIFOs for DAC and ADC paths so that they work at l_clk or l_clk/2
2017-01-18 12:01:24 +02:00
Istvan
06aab8ebbd
pzsdr1: Set the device core to 1R1T mode
2016-12-09 16:35:46 +02:00
Istvan
23c91ca48a
pzsdr1/lvds: The interface runs at max 122.88 MHz
2016-12-09 11:45:11 +02:00
Adrian Costina
0faa1ebff2
pzsdr1: ccusb_lvds, add flag_a,flag_b signals
2016-11-30 17:38:04 +02:00
Adrian Costina
8c4279f618
pzsdr1: Added ccusb_lvds initial project
2016-11-22 16:58:34 +02:00
Rejeesh Kutty
935f8a5c7b
pzsdr1/ccbox- constraints
2016-11-17 16:13:53 -05:00
Rejeesh Kutty
a61da1d2ac
pzsdr1/common- updates
2016-11-17 15:31:25 -05:00
Rejeesh Kutty
aa02ca875f
pzsdr1- common files
2016-11-17 13:40:25 -05:00
Rejeesh Kutty
8c25402d53
pzsdr1- common files
2016-11-17 13:40:04 -05:00
Rejeesh Kutty
918ce45e2a
pzsdr1/ccbox- updates
2016-10-17 16:29:57 -04:00
Rejeesh Kutty
cb97bc500a
hdlmake updates
2016-10-17 16:29:57 -04:00
Rejeesh Kutty
950acaed15
ccbox- copy
2016-10-17 16:29:57 -04:00
Rejeesh Kutty
bb62f6d225
pzsdr1- updates
2016-02-02 12:34:09 -05:00
Rejeesh Kutty
bcac3eef4d
pzsdr1- initial commit
2016-01-25 16:07:33 -05:00