665bfbc991
axi_ad7616: Add M_AXIS_READY_ENABLE parameter
...
m_axis_ready can be driven by the DMA or can have a constant active state. By default is always one.
2016-03-15 18:38:55 +02:00
334fce03a3
fmcadc4/zc706: Updated design to 2015.4
2016-03-15 15:28:11 +02:00
e8dd5f9788
fmcadc4: Updated common design to 2015.4
2016-03-15 15:27:25 +02:00
98cc7dad7d
fmcadc2: Updated common design to 2015.4
2016-03-15 15:26:05 +02:00
ceea7f25b2
fmcomms2: Updated common design to 2015.4
2016-03-15 15:23:20 +02:00
6f03998b95
zc702: Updated common design to 2015.4
2016-03-15 15:21:22 +02:00
a0c5f46940
zed: Updated common design to 2015.4
2016-03-15 15:20:46 +02:00
9a258d5e4c
vc707: Updated common design to 2015.4
2016-03-15 15:20:02 +02:00
bcf5bd8137
mitx045: Updated common design to 2015.4
2016-03-15 15:18:31 +02:00
27f5f1dcbe
kc705: Updated common design to 2015.4
2016-03-15 15:17:53 +02:00
eb743e0e03
ac701: Updated common design to 2015.4
2016-03-15 15:17:02 +02:00
d282064103
zc706: Updated common design to 2015.4
2016-03-15 15:16:36 +02:00
71be9519ec
adi_project.tcl: Updated to 2015.4
2016-03-15 15:03:50 +02:00
9b2a106aa0
axi_jesd_gt: changed clock and reset naming to be consistent with the other projects
2016-03-15 11:20:31 +02:00
06b7916303
axi_spdif_tx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:18:25 +02:00
ef05642e26
axi_spdif_rx: changed adi_ip_properties_lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:14:05 +02:00
b3ed38107c
axi_i2s_adi: changed adi_ip_properties lite to adi_ip_properties, so that the axi interface can be inferred
2016-03-15 10:12:45 +02:00
8ecf5edaf8
ad9122- pat modes
2016-03-14 11:14:29 -04:00
31cc91d1b9
adi_ip: Updated to 2014.4.2
...
- automatically infer clocks, resets, axim_mm and axis interfaces
2016-03-14 15:14:18 +02:00
33b265a742
Makefile: Update Makefiles
2016-03-14 09:31:17 +02:00
561412e322
pzsdr-cmos swap
2016-03-11 11:25:58 -05:00
c7ee15d4f4
ccbrk_cmos: cmos mode
2016-03-11 11:25:58 -05:00
c566784ba9
ccbrk_cmos: ccbrk copy
2016-03-11 11:25:58 -05:00
573146aa96
axi_ad7616: Fix the data width of the AXI stream interface
2016-03-10 16:38:53 +02:00
287770a201
axi_dmac: Fix tlast generation on AXI stream master
...
For the AXI stream interface we want to generate TLAST only at the end of
the transfer, rather than at the end of each burst.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-03-08 10:53:59 +01:00
2524f19ae0
Updated interfaces Makefile and Makefiles for the libraries that depend on it
2016-03-07 12:31:41 +02:00
b0f90bd0e8
daq1/cpld: Read interface fix
2016-03-04 20:28:24 +02:00
7e607957ee
daq1.cpld: Prevent the spi_counter to roll over.
2016-03-04 20:28:22 +02:00
262a42c676
daq1/cpld: Update CPLD_VERSION value
2016-03-04 20:28:20 +02:00
9439862301
daq1/cpld: Update CPLD
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Change to control line fpga_to_cpld to cpld_to_fpga, this is not a functional change.
2016-03-04 20:28:18 +02:00
583ef82fd0
ad9361- cmos mode
2016-03-04 10:39:48 -05:00
7a320a3d34
ad_lvds* - updates
2016-03-04 10:39:48 -05:00
3466f21f8e
pzsdr add cmos/lvds support
2016-03-04 10:39:48 -05:00
18f30c8dc8
pzsdr- cmos/lvds split
2016-03-04 10:39:48 -05:00
a2374f64bf
pzsdr- cmos/lvds split
2016-03-04 10:39:48 -05:00
7d2939be92
ad9361- cmos mode initial commit
2016-03-04 10:39:48 -05:00
977d9d0624
Merge branch 'hdl_2015_r2' into dev
...
Conflicts:
projects/daq1/common/daq1_spi.v
2016-03-02 13:52:15 +02:00
40fb68dfd5
ad9265, ad9434, ad9467, daq1, daq2, daq3, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1, fmcomms6, fmcomms7, usdrx1: updated common spi module so that spi streaming is possible
2016-03-02 13:39:37 +02:00
becc23a69b
daq2: Modified common spi module so that spi streaming is possible
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- stop incrementing spi_count after the instruction cycle
2016-03-01 17:25:58 +02:00
f7e490c2b3
hdlmake.pl updates
2016-02-26 13:46:11 -05:00
e012d0519b
Merge remote-tracking branch 'origin/hdl_2015_r2' into dev
2016-02-26 13:39:39 -05:00
f6e64e42b0
kcu105: add ethernet idelaycntrl
2016-02-26 13:19:49 -05:00
59313f3c90
daq1: ADC DMA must be in none-cyclic mode
2016-02-24 14:37:19 +02:00
c0a559a9b1
daq1: Fix some typos in the SPI wrapper
2016-02-24 14:31:56 +02:00
8ccd8d87bb
daq2: A10GX, increase analog/digital reset durations
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- reset the xcvr_rst_cntrl only from the axi_jesd_xcvr
- checked separate RX/TX reset per channel
2016-02-23 11:41:38 +02:00
89f7aadfb1
fmcjesdadc1: A5GT, connected xcvr_rxt_cntrl reset input to the axi_jesd_xcvr reset output
...
This will allow for the transceivers to be reset by the axi_jesd_xcvr core
2016-02-23 11:31:07 +02:00
4fb6589b2d
pzsdr/ccfmc: add fan controls
2016-02-19 16:40:54 -05:00
377461e0d4
Merge branch 'hdl_2015_r2' into dev
2016-02-19 14:15:27 +02:00
0f37dd6424
fmcjesdadc1: Fixed project
...
- changed system_project.tcl so that all base designs to be included
- changed DMA properties to take into consideration the new parameter names
- changed reset bridges to asynchronous
- increased maximum burst size of the DMA bridge
- changed the data_width of the memory bus to 256, as with 512 timing violations may occur
- changed base addresses for the base system to be the same as in the previous release
2016-02-19 14:09:57 +02:00
ce760eb691
fmcadc2- add adf4355 access
2016-02-18 16:17:33 -05:00
Istvan Csomortani
AndreiGrozav
Rejeesh Kutty
Adrian Costina
Lars-Peter Clausen