Due to nets being optimized at IP-level during the no-OOC synthesis flow,
constraints related to req_clk (request clock) were not being applied,
causing the design to not meet timing.
The fix considers the synchronous modes, appending the possible resulting
req_clk's names after the synthesis flow.
Due to grounded signals in the DMA_TYPE_SRC != DMA_TYPE_STREAM_AXI config.,
sync_rewind is removed during synthesis, even so, constraints were
trying to be applied to those nets.
To resolve this, sync_rewind block was moved to inside the generate.
Vivado seems to properly suppress "Empty list" warnings when the circuit does not exist because of a generate rule.
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>
- Removes the reset_tx_pll_and_datapath_in reset
- Connects gtreset_in to make use of the master reset found inside
the Transceiver Bridge IP
- Connects the necessary signals for the master reset between the
Transceiver Wizard and Transceiver Bridge
ad9209/vck190/system_top: Connect versal transceiver reset
Signed-off-by: Bogdan Luncan <bogdan.luncan@analog.com>
The following CWs appeared (even in Vivado version 2021.2):
* CRITICAL WARNING: [BD 41-1356] Slave segment </sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM> is not assigned into address space </axi_rd_wr_combiner_logic/m_axi>. Please use Address Editor to either assign or exclude it.
* CRITICAL WARNING: [BD 41-1356] Slave segment </sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM> is not assigned into address space </axi_rd_wr_combiner_converter/m_axi>. Please use Address Editor to either assign or exclude it.
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
Add a list with make commands with the proper parameters for each devicetree
availible at the moment.
Signed-off-by: LIacob106 <liviu.iacob@analog.com>
* Updated the versions for repos and this solved the deprecated command
issue
* Changed the end message for when the guideline is not followed
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
The ADI_EXTRACT_PORTS variable is used to extract all the ports and nets properties of the desired IPS for the TransceiverToolbox and HighSpeedConverterToolbox to be later used for generating the json files automatically.
The ADI_SKIP_SYNTHESIS variable is used to stop the building process before the synthesis when used with Matlab support as it is not necessary at this point.
The ADI_MATLAB variable is used to choose the correct paths when building the design when using the HWA workflow.
docs/regmap/adi_regmap_adc.txt:
- add softspan to regmap
library/common/up_adc_channel.v
- update copyright year header
- add softspan to regmap
library/common/up_adc_common.v
- update minor version
Signed-off-by: John Erasmus Mari Geronimo <Johnerasmusmari.Geronimo@analog.com>
* ad_data_in: Add new logic and explanations
* Added parameters IDELAY_TYPE, DELAY_FORMAT, US_DELAY_TYPE to be used
with the IDELAY instances
* Added explanations
* Added option to bypass IDELAY if it's not instantiated, regardless of
the FPGA_TECHNOLOGY parameter
* Determined a part of the logic for EN_VTC (by the UG) but not for all
modes since we don't have use cases for them
* Changed logic when adding ODELAY: now you must set IODELAY_ENABLE = 1
and FPGA_TECHNOLOGY != NONE if you want it
* ad_data_out:
* Updated ODDR parameter
* Fixed issue with ODDR inputs D1, D2: D1 must be with _p and D2 with _n,
according to the Xilinx template
* Removed _ES1 from IODELAY_SIM_DEVICE
* Added ODELAY for UltraScale
* Before, there was no support for UltraScale/+, and the output data
was completely disconnected from the ODDR
* The support for this was requested in this issue, although as of now we don't
have a design that uses it: https://github.com/analogdevicesinc/hdl/issues/917
* Added parameters ODELAY_TYPE, DELAY_FORMAT, US_DELAY_TYPE to be used
with the ODELAY instances
* Added explanations
* Added option to bypass ODELAY if it's not instantiated, regardless of
the FPGA_TECHNOLOGY parameter
* Determined a part of the logic for the EN_VTC (by the UG) but not for
all modes since we don't have use cases for them
* Changed logic when adding ODELAY: now you must set IODELAY_ENABLE = 1
and FPGA_TECHNOLOGY != NONE if you want it
---------
Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
The SPI Engine cores were named directly inside the script and this
would mean that for multiple SPI Engine instances IPs with the same
name would appear. These updates will introduce the hierarchy name
into the name given to the cores and will therefore allow for
multiple instances of SPI Engine to be added to the same Xilinx
project.
Projects which use spi_engine.tcl will be updated to account for
these changes.
- Quartus version was updated
- the start_n output port was deteled from system_top.v
- the ""mixed_port_feed_through_mode" parameter of RAM can not have value "old"" warning was disabled
- update Makefile copyright year
Signed-off-by: Paul Pop <paul.pop@analog.com>
bug:
say "make LVDS_CMOS_N=0"
- will set ad_project_dir as LVDSCMOSN0
- will then set system_qip_file as LVDSCMOSN0/system_bd/synthesis/system_bd.qip
- build error reveals system_bd can't be found
- maybe due to setting ad_project_dir as a relative file path
fix:
- set ad_project_dir as an absolute file path
Signed-off-by: Jem Geronimo <Johnerasmusmari.Geronimo@analog.com>
Iulia Moldovan
Jorge Marques
AndreiGrozav
Bogdan Luncan
alin724
LIacob106
Filip Gherman
PIoandan
Stanca Pop
Jem Geronimo
ladace
AndrDragomir
imoldovan
sergiu arpadi
laurent-19
Paul Pop