cd29807edc
Revert "altera/ad_serdes: Fix net alignment for rx_out at ad_serdes_in"
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This reverts commit 0715c962f1
2017-06-29 09:25:04 +01:00
25a9949899
util_clkdiv: Register output port as a clock ( #33 )
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If the output pin is not defined as a clock, some of the Vivado IPI
propagation TCL will error out.
Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
2017-06-19 07:40:53 +01:00
e99244b041
axi_ad9739a: Fix DDS set frequency
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- DDS out frequency was 4 times greater than the desired frequency
2017-05-10 17:30:15 +03:00
d3c6771ad6
axi_ad9371: Update dac_clk_ratio to 2
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DAC sampling frequency is two times of the JESD204
core clock.
2017-05-10 11:36:07 +03:00
e2ef470150
axi_ad9434: Fix input data rate
2017-05-04 16:38:21 +03:00
edefb9df44
axi_hdmi_tx: Fix assignment type
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The general rule of thumb is to use nonblocking assignments for
sequential always blocks.
2017-04-21 09:06:54 +03:00
54ff4d7bd0
ad_serdes_in: Fix generate block
2017-04-20 19:47:45 +03:00
7659700719
ad_serdes_clk: Fix generate block
2017-04-20 19:47:19 +03:00
03dcbc6a7d
ad_mmcm_drp: Fix generate block
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Can not be multiple 'if' statements inside a generate block. If there are
multiple cases use if/esle statement, but always should be one single
if/else inside a generate.
2017-04-20 19:43:46 +03:00
ee398b4703
spi_engine: Fix CMD_FIFO_VALID generation
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Because of the memory map interface mux, up_waddr_s and up_wreq_s should be
used, when cmd_fifo_in_valid is generated.
2017-04-12 14:43:00 +02:00
75409eeb38
util_fir_int: Shifted data so that the amplitude at the output of the filter is the same with the input
2017-04-12 13:49:53 +03:00
096aadbf91
util_fir_dec: Changed output rounding mode to Symmetric rounding to Zero
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This removes the added DC component that was introduced by the previous rounding mode
2017-04-12 13:49:37 +03:00
f7190dbbfd
adxcvr: Update Makefiles
2017-04-03 12:38:40 +03:00
fa5f81f6c6
axi_dacfifo: Fix clock for read address generation
2017-04-03 10:39:17 +03:00
7cb7bc111e
axi_dacfifo: Delete unused wires
2017-04-03 10:38:50 +03:00
14b4c4cf5f
axi_dacfifo: Define constraint for bypass
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The bypass module currently is supported, when the DMA data width
is equal with the DAC data width.
The dac_data output is enabled with dac_valid.
2017-04-03 10:38:28 +03:00
06605ed1e1
axi_dacfifo: Register the dac_valid signals
2017-04-03 10:38:09 +03:00
77081a6233
axi_dacfifo: Data from DMA is validated with dma_ready too
2017-04-03 10:37:45 +03:00
af3a4f5fc9
axi_dacfifo: axi_dvalid should come from dacfifo_rd module
2017-04-03 10:37:30 +03:00
b30041f7f3
axi_dacfifo: Redesign the bypass functionality
2017-04-03 10:37:08 +03:00
434d1ea52c
axi_dacfifo: Fix constraints
2017-04-03 10:36:46 +03:00
981a61bf16
axi_dacfifo: Clean up the axi_dacfifo_wr.v module
2017-02-17 18:40:02 +02:00
f10866e4c3
axi_*fifo: Delete/replace AXI_BYTE_WIDTH parameter
2017-02-16 19:54:41 +02:00
95a4ea20c8
axi_dacfifo: Delete redundant parameter BYPASS_EN
2017-02-16 19:53:44 +02:00
358aa48c76
axi_adc_decimate: Fix assignment width
2017-02-15 11:38:43 +02:00
c6ee76421b
axi_usb_fx3: Fixed clock domain association
2017-02-14 11:48:07 +02:00
7c86b038ef
util_fir_int: manually request data at 1/8 clock frequency
2017-02-13 18:05:59 +02:00
5fa6dba333
Make: Update Makefiles
2017-02-10 16:32:58 +02:00
0dae754f2d
axi_adxcvr: Add rparam register to Altera XCVR
2017-02-10 16:19:17 +02:00
24daffcf5c
spi_engine: Set up default driver value for input ports
2017-02-07 12:30:46 +02:00
47db0d80fe
axi_ad7616: Set up default driver value for input ports
2017-02-07 12:29:21 +02:00
a57fb5f82f
library/ad9122- constraints clean-up
2017-02-02 14:21:41 -05:00
1e54b5230f
axi_adxcvr- add m_axi associated clock
2017-02-02 11:17:56 -05:00
806d19febc
axi_adxcvr- add primitive info read
2017-02-01 13:38:29 -05:00
1c9d8c4e7c
axi_adxcvr- add primitive info read
2017-02-01 13:35:02 -05:00
1df6178ab8
library: Update common Makefile
2017-01-31 16:44:32 +02:00
7387df9d13
util_var_fifo: Initial commit
2017-01-31 16:26:45 +02:00
b9c94f63a5
util_extract: Initial commit
2017-01-31 16:26:05 +02:00
6604cc7322
axi_logic_analyzer: Initial commit
2017-01-31 16:23:56 +02:00
9c975211da
axi_dac_interpolate: Initial commit
2017-01-31 16:22:49 +02:00
4a7232cbcb
axi_adc_decimate: Initial commit
2017-01-31 16:21:39 +02:00
35b97abc6d
axi_adc_trigger: Initial commit
2017-01-31 16:20:13 +02:00
fb945ac51c
axi_ad9963: Initial commit
2017-01-31 16:18:58 +02:00
d5af828b9c
Merge branch 'dev' into hdl_2016_r2
2017-01-30 17:10:05 +02:00
db924953bb
altera- warnings about init values
2017-01-30 10:01:28 -05:00
eb8a3fff3c
axi_dmac: Set IP core name and description
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Add a human readable name and descriptor for the AXI DMAC core.This string
will appear in various places e.g. like the IP catalog. This is a purely
cosmetic change.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-01-30 13:58:48 +01:00
3dd736fe8c
axi_dmac: Add identification register
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Add a register to the AXI DMAC register map which functions has a
identification register. The register contains the unique value of "DMAC"
(0x444d4143) and allows software to identify whether the peripheral mapped
at a certain address is an axi_dmac peripheral.
This is useful for detecting cases where the specified address contains an
error or is incorrect.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-01-30 13:58:48 +01:00
3f3a8bd267
library: forced ad_mem module to be implemented in BRAM for Xilinx devices
2017-01-25 18:12:04 +02:00
c8b638e182
ad9152- add prbs generators
2017-01-23 10:31:57 -05:00
a2b2ebbed2
ad_lvds_in- ultrascale/ultrascale+ sim device mess
2017-01-21 20:54:21 -05:00
Andrei Grozav
Matthew Fornero
Istvan Csomortani
Adrian Costina
Rejeesh Kutty
Lars-Peter Clausen