Commit Graph

10 Commits (cb3d1883bc59b418fa45cc04da6cd0466d3502ac)

Author SHA1 Message Date
Rejeesh Kutty a2b2ebbed2 ad_lvds_in- ultrascale/ultrascale+ sim device mess 2017-01-21 20:54:21 -05:00
Rejeesh Kutty cc6ca4f0f2 ad_lvds_in- ultrascale sim device 2016-10-10 10:39:47 -04:00
Istvan Csomortani ff980551e6 ad_serdes: SERDES_FACTOR handover missing
In modules ad_serdes_in/ad_serdes_out the handover of the parameter
SERDES_FACTOR did not exist, causing unwanted behavioral in case of
factors less than 8.
SERDES_FACTOR must be hand over to DATA_WIDTH parameter of the SERDES
primitive.
2016-10-10 16:38:42 +03:00
Rejeesh Kutty 6b956066ef xilinx/ad_lvds*- ultrascale+ 2016-09-30 11:55:10 -04:00
Istvan Csomortani 38f1521861 xilinx/ad_serdes_in : Fix some typos 2016-09-19 16:02:52 +03:00
Istvan Csomortani ff0f659a33 xilinx/ad_serdes_clk : Rename parameter MMCM_DEVICE_TYPE to DEVICE_TYPE 2016-09-19 16:02:06 +03:00
Istvan Csomortani 6510f92c12 ad_serdes : Cosmetic changes 2016-09-16 14:45:39 +03:00
Rejeesh Kutty a2d15acb89 ad_serdes- altera/xilinx sync 2016-09-15 13:33:55 -04:00
Istvan Csomortani 1d33d7d7ee lib_refactoring: Move the CMOS interface modules to ~/library/xilinx/common 2016-08-08 15:07:42 +03:00
Istvan Csomortani b806fa3b42 lib_refactoring: Move all the Xilinx common modules to library/xilinx/common 2016-08-08 15:06:10 +03:00