Commit Graph

1815 Commits (cafa811c74b7ef2589438c1374d5b99e5d338d61)

Author SHA1 Message Date
Adrian Costina 9a32240cc5 axi_ad9379: Initial commit 2017-09-01 17:26:37 +03:00
Adrian Costina 6d5b5b50a5 axi_logic_analyzer: Compensate the 4 word latency of util_var_fifo 2017-08-30 18:17:41 +03:00
Adrian Costina f6288dc0a3 util_extract: Compensate 4 word latency 2017-08-30 18:02:09 +03:00
Adrian Costina 54e96c49ae util_var_fifo: Set fix latency of 4 for all interpolation values 2017-08-30 18:01:06 +03:00
Lars-Peter Clausen 3e96903be7 jesd204_rx: rx_ctrl: Fix typo
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-28 16:11:00 +02:00
Adrian Costina 421b4bed41 axi_ad9963: Moved RX configuration bit SCALECORRECTION_ONLY to bit 9 2017-08-28 15:58:00 +03:00
Rejeesh Kutty f19b8c62a1 library- add a timer for quick start 2017-08-25 13:28:05 -04:00
Rejeesh Kutty 4050f5ae58 adrv9361- add adl5904 2017-08-24 15:47:17 -04:00
Lars-Peter Clausen e4bb2beaf1 altera: adi_jesd204: Export link domain reset
Export the reset signal for the link clock domain. This can be used by
external logic that is in the link clock domain to reset itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:43:12 +02:00
Lars-Peter Clausen 853342b201 altera: adi_jesd204: Disable FPLL phase alignment mode
Enabling the phase alignment mode of the FPLL seems to break manual
re-calibration, which is required when changing the lane rates. The
calibration seems to select the wrong VCO frequency band and the PLL no
longer locks.

Disable phase alignment mode for now, this has a negative effects on
deterministic latency, but it is better than not working at all.

Waiting for feedback from Altera/Intel on how to make manual re-calibration
work in phase alignment mode.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:43:12 +02:00
Lars-Peter Clausen 72a23eeb71 altera: adi_jesd204: Enable avmm_busy flag in the link FPLL register map
To be able to check the FPLL re-configuration arbitration status from
software enable the avmm_busy flag in the register map.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:42:44 +02:00
Lars-Peter Clausen dd1b1c89f9 jesd204: jesd204_rx: Don't expose internal states on the status interface
The DEGLITCH state of the RX state machine is a workaround for misbehaving
PHYs. It is an internal state and an implementation detail and it does not
really make sense to report through the status interface.

Rework things so that DEGLITCH state is reported as part of the CGS state
on the external status interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:42:44 +02:00
Lars-Peter Clausen e6aacd2f56 axi_dmac: Better support debug IDs when ID_WIDTH != 3
The current layout of the debug ID register assumes that the ID_WIDTH is 3.
Change things so that the padding 0 width depends on the ID_WIDTH
parameter so that we end up with the same register layout regardless of the
value of ID_WIDTH.

Also split things into two registers, this allows for an ID_WIDTH up to 8
(which should hopefully be enough for all practical applications).

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:42:20 +02:00
Istvan Csomortani deefb33490 avl_dacfifo: Update IP to qsys flow 2017-08-22 09:16:21 +01:00
Istvan Csomortani b2550b7aa0 axi_dacfifo: Update constraints 2017-08-22 09:16:21 +01:00
Istvan Csomortani 85a7cebc0e axi_dacfifo: Major update and redesign
Redesign the axi_dacfifo, to increase the supported datarates.
Major modifications:
  + The FIFO consist of two module: WRITE and READ. The axi_dacfifo_dac
was deprecated.
  + Both the AXI write and AXI read transaction are controlled by two
FSM, to increase redability of the code.
  + Support all the possible burst lengths [0..225], handles the last
fractional burst on both sides correctly.
  + Common reset architecture throughout the design, all the internal
registers and memories are reset on the posedge of dma_xfer_req
  + Delete all Altera related sources, for Altera projects
avl_dacfifo should be used.

WIP: foobar

[WIP]axi_dacfifo: Update

axi_dacfifo: Few minor updates, almost working state
2017-08-22 09:16:21 +01:00
Lars-Peter Clausen 4de0a94e37 altera: jesd204_phy: Fix indention issues
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 13:57:55 +02:00
Lars-Peter Clausen 9c5b48c151 library: Add ADI JESD204 wrapper for Altera/Intel platforms
Add a wrapper module for Altera/Intel platforms that instantiates and
connects all the components required to for a JESD204 link.

The following components are created:
  * Transceiver for each lane
  * Transceiver lane PLL (TX only)
  * Transceiver reset controller
  * Link PLL
  * JESD204 link layer processing
  * JESD204 link layer processing control interface
  * axi_adxcvr link management peripheral

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:21:42 +02:00
Lars-Peter Clausen 0108d01043 library: Add JESD204 PHY wrapper for Arria10 Native PHY
Add a wrapper that instantiates the Arria10 Native PHY and configures it
for JESD204 operation. The datapath width is set to 4 octets per beat.

The maximum lane rate that is achievable with hard-logic PCS included in
the PHY is below the requirements of the JESD204 for some of the PHY speed
grades. For projects that require a lane rate that is higher than what the
hard-logic PCS can support a soft-logic PCS module can be instantiated. The
external interface of the jesd204_phy is identical regardless of whether
soft- or hard-logic PCS is used.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:20:57 +02:00
Lars-Peter Clausen 4df841addc jesd204: Add soft logic PCS
Add soft logic PCS that performs 8b10b encoding for TX and character
pattern alignment and 8b10b decoding for RX.

The modules are intended to be used in combination with a transceiver that
does not have these features implemented in hard logic PCS.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:09:42 +02:00
Lars-Peter Clausen 2d896c0729 jesd204: Add Altera/Intel IP support
Add Qsys IP scripts as well as SDC constraint files for the ADI JESD204
peripherals. This allows them to be instantiated and used on Altera/Intel
platforms.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:09:42 +02:00
Lars-Peter Clausen d345a1e31a jesd204: jesd204_tx: Add dummy valid for the TX data interface
The Xilinx tools are quite forgiving when it comes to required signals on
standard interfaces, which is why it was possible to define a AXI streaming
interface without the required valid signal.

The Altera tools are more strict and wont allow this. Add a dummy valid
signal to the TX data interface to make the tools happy. For now the signal
does not do anything, in the future it might be used to detect an underflow
condition on the data interface and report this through the status
interface.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:08:27 +02:00
Lars-Peter Clausen f730f14d16 jesd204: ilas_mem: Rework to be more Altera friendly
Currently the ILAS memory for the receive register map uses a shift
register with variable tap output for storing the ILAS information. This
maps very efficiently onto the primitives found in Xilinx FPGAs. But there
is no equivalent primitive in Altera FPAGs resulting in increased
utilization from having to implement the structure in pure logic.

Change the ILAS memory so it uses a simple dual port RAM for storing the
data. This has slightly increased utilization on Xilinx platforms (but
still good enough) and highly decreased utilization on Altera platforms.

One side effect of this change is that since the RAM output is synchronous
reading the ILAS memory registers will take one extra clock cycle.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:05:16 +02:00
Lars-Peter Clausen 2d2477e552 util_cdc: Add helper function for creating constraints for the CDC blocks
Add a set of helper functions for the CDC library that creates the correct
constraints for the CDC blocks. This makes it easier to specify the
constraints in the individual user's SDC files.

This only works for Altera where full scripting capabilities are available
in the SDC files.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:05:16 +02:00
Lars-Peter Clausen 27d243ad14 adi_ip_alt.tcl: ad_ip_parameter: Allow to specify additional properties
Allow to specify additional properties when defining a IP parameter. The
properties take the form of a list of key value pairs. E.g.

ad_ip_parameter ... { \
  DISPLAY_NAME "Name" \
  DISPLAY_HINT "radio" \
}

This helps to reduce the amount of boilerplate when additional properties
need to be specified for a parameter.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:05:16 +02:00
Lars-Peter Clausen 9bf852fff2 adi_ip_alt.tcl: Allow to add TCL files to the fileset
TCL files can be helpful to automate certain tasks like creating timing
constraints. Add handling for them to the ad_ip_addfile function.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:05:16 +02:00
Lars-Peter Clausen 4acb91bedb jesd204: axi_jesd204_{rx,tx}: Add external link domain reset
Currently the reset for the link clock domain is generated internally in
the axi_jesd204_{rx,tx} peripheral. The reset is controlled by through the
register map.

Add an additional external reset for link clock domain. The link clock
domain is kept in reset if either the internal reset or the external reset
is asserted.

This for example allows the fabric to keep the domain in reset if the clock
is not yet stable.

The status of the external reset can be queried from the register map.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-18 18:25:12 +02:00
Lars-Peter Clausen cefb2b062e util_adcfifo: Remove always false check
dma_raddr is only incremented if it is less than dma_waddr_rel_s.
dma_waddr_rel_s is always less or equal to adc_waddr_rel << RATIO and
adc_waddr_rel is less than DMA_ADDR_LIMIT >> RATIO.

By induction we can conclude that this means that dma_raddr will always be
less then DMA_ADDR_LIMIT and the check for this will always evaluate to
false can be removed.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-18 09:26:24 +02:00
Lars-Peter Clausen a46b9cfa5a util_adcfifo: Fix data corruption at faster DMA clock rates
When the DMA clock to ADC data rate ratio exceeds a certain threshold it is
possible that an erroneous dma_waddr_rel toggle event is generated. This
causes the last address of the previous DMA transfer to be transferred to
the DMA domain. And the DMA side will start reading from the FIFO even
though data is not available yet.

This results in data corruption with the current transfer containing data
from the previous transfer.

The root cause here is that the toggle signal CDC synchronizer register are
reset in the DMA when a new transfer starts, but not in the ADC domain,
causing a potential mismatch and the incorrect toggle event. To fix this
remove the reset from the DMA side. This is OK since the registers are
self-resetting if the reset signal is asserted for more than 3 clock cycles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-18 09:26:23 +02:00
Lars-Peter Clausen f9fe66694d axi_logic_anlayzer: Fix trigger AND logic
AND logic means that all enabled triggers need to evaluate to true, others
are don't care. Fix the logic to behave accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-17 11:36:56 +02:00
Lars-Peter Clausen 42ff5d4f80 axi_streaming_dma_tx_fifo: Fix drain logic
At the moment the drain signal is always asserted when the controller is
enabled. This breaks backpressure and data is lost. The drain signal should
only be asserted when the controller gets disabled until the last beat of
the current DMA transfer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-14 16:02:32 +02:00
Lars-Peter Clausen 38f495b2cf axi_i2s_adi: Make constraints work on UltraScale
The 'PRIMITIVE_SUBGROUP == flop' filter only works on 7-Series. Replace it
with 'IS_SEQUENTIAL' which works on both 7-Series and UltraScale.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-14 16:02:32 +02:00
Lars-Peter Clausen 3ab3d3d111 jesd204: axi_jesd204_rx_regmap_tb: Add missing dependency
Add missing source file dependency for the axi_jesd204_rx_regmap_tb.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-13 10:28:11 +02:00
Lars-Peter Clausen d807b10632 axi_dmac: axi_dmac_hw.tcl: Set associated reset and addressable point for the interrupt interface
Altera recommends to set those properties for better qsys integration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-13 10:28:11 +02:00
Lars-Peter Clausen 8dc2161870 alt_mem_asym: Set read latency to 1 clock cycle
In its default configuration the ram_2port module as a read latency of 2
clock cycles. Both the read address as well as the output data are
registered.

This is not the behavior that is expected from the alt_mem_asym module and
causes incorrect behavior and data corruption in the util_adc_fifo.

Disable the data output register to get a read latency of 1 clock cycle.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-13 10:28:11 +02:00
Rejeesh Kutty bb660d8cf8 rfifo- drive valid outs 2017-08-10 11:23:40 -04:00
Rejeesh Kutty 8aba66477e util_adxcvr- defaults for es 2017-08-08 11:03:38 -04:00
Rejeesh Kutty 1c386d4d34 hdlmake.pl- updates 2017-08-07 16:09:20 -04:00
Lars-Peter Clausen 2b84fbb3b3 jesd204: Use consistent naming scheme for CDC blocks
Name all CDC blocks following the patter i_cdc_${signal_name}. This makes
it clear what is going on.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:44:23 +02:00
Lars-Peter Clausen 918f226f3b jesd204_tx: Use the CDC sync_bits helper to synchronize the SYNC~ signal
Use the CDC sync_bits helper to synchronize the asynchronous external SYNC~
signal into the link clock domain, rather than open-coding this operation.

This makes it more explicit what is going on.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:44:23 +02:00
Lars-Peter Clausen 350fbacf94 axi_jesd204_tx: Remove IRQ events for now
Which events will be exposed as IRQs and at what level of granularity will
need some additional through. Remove the two existing IRQ events for now
again. This will be added back later.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:44:23 +02:00
Lars-Peter Clausen 533b27bb13 axi_jesd204_tx: jesd204_up_tx: Use two dimensional array for up_cfg_ilas_data
The up_cfg_ilas_data signal is a two dimensional array. There are 4
register entries for each lane. Model it as such rather than compressing it
down to a one dimensional array. This makes accessing the individual
entries a bit more straight forward and the code clearer.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:42:56 +02:00
Lars-Peter Clausen 5d66f1d7bb jesd204_tx: Remove duplicated file
The ilas_cfg_static.v is part of the jesd204_tx_static_config module.
Somehow a copy of that file made it into the jesd204_tx module where it is
completely unused. Remove the duplicated file.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:42:17 +02:00
Lars-Peter Clausen a4641d99ba jesd204: rx_tb: Fix some incorrect signal connections
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:42:17 +02:00
Lars-Peter Clausen c51517f548 axi_adxcvr: Avoid implicit signal truncation warning
We know that NUM_OF_LANES will never exceed 255, but the tools don't know
and generate a warning about implicit signal truncation. Make the
truncation explicit to indicate that this is intentional.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-07 17:42:17 +02:00
Istvan Csomortani 9db58f5bb0 axi_ad9671: Fix typo 2017-08-07 10:54:45 +01:00
Istvan Csomortani 3b6f1e402a axi_ad9625: Fix typo 2017-08-07 10:53:57 +01:00
Istvan Csomortani fb6035f0dc util_cdc: Update to verilog-2001 coding standard 2017-08-07 11:26:17 +03:00
Istvan Csomortani 915fe036f2 util_axis_resize: Coding style updates
+ update to verilog-2001 coding standard
  + define RATIO outside the generate block
  + $clog2 macro is not supported by some tools, define function
locally
2017-08-07 11:23:57 +03:00
Istvan Csomortani 420245337d axi_ad9361: Update constraint file
Timing constraints, related to the PPS receiver, should be applied just
when the module is instantiated into the core.
2017-08-04 16:20:33 +01:00