Commit Graph

6 Commits (ca813974100267c9c1eebec50ae4d098e5dea40a)

Author SHA1 Message Date
Lars-Peter Clausen cdf2150128 altera: jesd204: Add support for lane polarity inversion
Some designs choose to swap the positive and negative side of the of the
JESD204 lanes. One reason for this would be because it can simplify the
PCB layout. The polarity is in most cases also only applied to a subset of
the used lanes.

Add support for this to the adi_jesd204 and jesd204_phy for Altera modules.
This done by adding new parameter to the modules that allows to specify a
per lane polarity inversion. Each bit in the parameter corresponds to one
lane. If the bit is set the polarity is inverted for his lane. E.g. setting
the parameter to 0xc will invert the 3rd and 4th lane.

The setting is forwarded depending on whether soft or hard PCS is used to
either the soft PCS module or the transceiver block itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-05-02 09:37:23 +02:00
Adrian Costina 1b1edd1b03 jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps 2017-10-25 14:36:54 +01:00
Lars-Peter Clausen e4bb2beaf1 altera: adi_jesd204: Export link domain reset
Export the reset signal for the link clock domain. This can be used by
external logic that is in the link clock domain to reset itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:43:12 +02:00
Lars-Peter Clausen 853342b201 altera: adi_jesd204: Disable FPLL phase alignment mode
Enabling the phase alignment mode of the FPLL seems to break manual
re-calibration, which is required when changing the lane rates. The
calibration seems to select the wrong VCO frequency band and the PLL no
longer locks.

Disable phase alignment mode for now, this has a negative effects on
deterministic latency, but it is better than not working at all.

Waiting for feedback from Altera/Intel on how to make manual re-calibration
work in phase alignment mode.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:43:12 +02:00
Lars-Peter Clausen 72a23eeb71 altera: adi_jesd204: Enable avmm_busy flag in the link FPLL register map
To be able to check the FPLL re-configuration arbitration status from
software enable the avmm_busy flag in the register map.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-24 17:42:44 +02:00
Lars-Peter Clausen 9c5b48c151 library: Add ADI JESD204 wrapper for Altera/Intel platforms
Add a wrapper module for Altera/Intel platforms that instantiates and
connects all the components required to for a JESD204 link.

The following components are created:
  * Transceiver for each lane
  * Transceiver lane PLL (TX only)
  * Transceiver reset controller
  * Link PLL
  * JESD204 link layer processing
  * JESD204 link layer processing control interface
  * axi_adxcvr link management peripheral

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:21:42 +02:00