pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Adrian Costina	ab8627e669	fmcomms1: Changed ILA data capture and sys constraints The ILA can not work at 250MHz on ZED/ZC702. Because of this, the data path was modified from 28bits@250MHz to 56bits@125MHz, by using a FIFO. The ZED/ZC702 max BUFG frequency is 464MHz, which corresponds to a 2.16 period so the constraints were modified accordingly.	2014-03-17 15:50:01 +02:00
Adrian Costina	92aaf0bd51	FMCOMMS1: Updated projects and axi_ad9643 core ZC702: Removed invalid address segments. Changed the constraints for adc_clk to minimum possible value in order to meet timing. ZED: Change the constraints for adc_clk to minimum possible value, in order to meet timing AXI_AD9643: Corrected the number of bits in the adc_mon_data bus	2014-03-12 16:23:41 +02:00
Rejeesh Kutty	f8ab734918	projects/fmcomms1: added	2014-03-11 12:16:25 -04:00

Author

SHA1

Message

Date

Adrian Costina

ab8627e669

fmcomms1: Changed ILA data capture and sys constraints

The ILA can not work at 250MHz on ZED/ZC702. Because of this, the data
path was modified from 28bits@250MHz to 56bits@125MHz, by using a FIFO.
The ZED/ZC702 max BUFG frequency is 464MHz, which corresponds to a 2.16
period so the constraints were modified accordingly.

2014-03-17 15:50:01 +02:00

Adrian Costina

92aaf0bd51

FMCOMMS1: Updated projects and axi_ad9643 core

ZC702: Removed invalid address segments. Changed the constraints
for adc_clk to minimum possible value in order to meet timing.

ZED: Change the constraints for adc_clk to minimum possible value, in
order to meet timing

AXI_AD9643: Corrected the number of bits in the adc_mon_data bus

2014-03-12 16:23:41 +02:00

Rejeesh Kutty

f8ab734918

projects/fmcomms1: added

2014-03-11 12:16:25 -04:00

3 Commits (ca7a70650d9aca6586bbc290786e767620fd4ff4)