Commit Graph

208 Commits (c9f1c92eaa79365ff262a4637b7b03bea90eaa3d)

Author SHA1 Message Date
Lars-Peter Clausen 9b919636ca fmcjesdadc1: Use new pack infrastructure
Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
Laszlo Nagy 4ce153e6e1 all/system_top.v: loopback gpio lines
Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
Laszlo Nagy 31318cf311 all/system_top.v: drive unused gpio inputs with zero
The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.

Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
Laszlo Nagy fa7c85a9eb all: Drive undriven input signals, complete interface
- connect unused GPIO inputs to loopback
- connect unconnected inputs to zero
- complete interface for system_wrapper instantiated in all system_top

fixes incomplet portlist WARNING [Synth 8-350]
fixes undriven inputs WARNING [Synth 8-3295]

The change excludes the generated system.v and Xilinx files.
2018-08-10 17:00:11 +03:00
AndreiGrozav ebae8bf8c1 Remove interrupts from system_top for all xilinx projects
- remove interrupts from system_top
- for all suported carriers:
	- remove all interrupt bd pins
	- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
Laszlo Nagy 1bd65da29f fmcjesdadc1: increase DMAC FIFO size
The DMAC FIFO ocasionally overflow, increased it's size to give more time
the MM interface to move out the data.
2018-05-23 13:10:12 +01:00
Istvan Csomortani 3ce9f55c39 fmcjesdadc1:a10: Move block design into feature branch
Move block design file into the fmcjesdadc1_a10 feature branch.
2018-04-13 17:37:17 +01:00
Istvan Csomortani 6419de60c4 fmcjesdadc1:altera: Move projects to a feature branch 2018-04-13 18:22:15 +03:00
Lars-Peter Clausen 2b914d33c1 Move Altera IP core dependency tracking to library Makefiles
Currently the individual IP core dependencies are tracked inside the
library Makefile for Xilinx IPs and the project Makefiles only reference
the IP cores.

For Altera on the other hand the individual dependencies are tracked inside
the project Makefile. This leads to a lot of duplicated lists and also
means that the project Makefiles need to be regenerated when one of the IP
cores changes their files.

Change the Altera projects to a similar scheme than the Xilinx projects.
The projects themselves only reference the library as a whole as their
dependency while the library Makefile references the individual source
dependencies.

Since on Altera there is no target that has to be generated create a dummy
target called ".timestamp_altera" who's only purpose is to have a timestamp
that is greater or equal to the timestamp of all of the IP core files. This
means the project Makefile can have a dependency on this file and make sure
that the project will be rebuild if any of the files in the library
changes.

This patch contains quite a bit of churn, but hopefully it reduces the
amount of churn in the future when modifying Altera IP cores.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen b7f8345f17 library: Remove unreferenced files from IP file lists
Some IP core have files in their file list for common modules that are not
used by the IP itself. Remove those.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen b20714bae2 Regenerate project top-level Makefiles
Removes a lot of boilerplate code.

Using the new scheme it is possible to add new projects or sub-projects
without having to re-generate any existing Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Lars-Peter Clausen 377247a434 Regenerate project Makefiles using the new shared Makefile includes
This reduces the amount of boilerplate code that is present in these
Makefiles by a lot.

It also makes it possible to update the Makefile rules in future without
having to re-generate all the Makefiles.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-04-11 15:09:54 +03:00
Istvan Csomortani 425e803364 license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
AndreiGrozav 502989c25f jesd_rst_gen:constraints: Remove invalid false path definitions
The constraint where added to remove timing problems on the reset path.

The constraint paths do not match anymore. The resets are used in a synchronous
way so we don't need the timing exceptions anyway.

Projects affected by this change:
  - daq3
  - adrv9739
  - ad6676evb
  - fmcadc5
  - daq2/kcu105
  - fmcadc2
  - adrv9371x
  - fmcomms11/zc706
  - fmcjesdadc1
2018-04-11 15:09:54 +03:00
Istvan Csomortani a740b6012f Make: Use $(MAKE) for recursive make commands
This commit should resolve the issue #64.

Recursive make commands should always use the variable MAKE, not the explicit
command name ‘make’.
2018-03-07 07:40:19 +00:00
Lars-Peter Clausen 8b6d69747b fmcjesdadc1: Fix OUT_CLK_SEL configuration
The script specifies the OUT_CLK_SEL and SYS_CLK_SEL parameter values as
binary numbers. But the tools will interpret them as decimal number
resulting in the wrong selection for OUT_CLK_SEL. Specify the parameter
values as decimal values to avoid this.

This is not a critical issue since software will overwrite this setting at
system boot-up. But it should be fixed anyway.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-16 13:32:50 +01:00
Lars-Peter Clausen ce8bcfd192 fmcjesdadc1: Remove wire that is a redeclaration of a port
Fixes the following warning:
	[Synth 8-2611] redeclaration of ansi port rx_sysref is not allowed

This is a leftover of commit 1c23cf4621 ("all: Update verilog files to
verilog-2001").

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-02-16 13:32:26 +01:00
Adrian Costina b54dab33e0 Make: Update makefiles 2017-11-20 14:27:39 +02:00
Adrian Costina 45f2fbf3c0 fmcjesdadc1: Update A10GX/A10SOC projects to the ADI JESD framework 2017-11-08 14:35:18 +02:00
Istvan Csomortani baf8ec09a3 fmcjesdadc1/a10gx: Add external flash support 2017-10-06 08:46:22 +01:00
Lars-Peter Clausen f0655e63a6 avl_adxcvr: Derive PLL and core clock frequency from lane rate
The PLL frequency must be half of the lane rate and the core clock rate
must be lane rate divided by 40. There is no other option, otherwise things
wont work.

Instead of having to manually specify PLL and core clock frequency derive
them in the transceiver script. This reduces the risk of accidental
misconfiguration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-28 15:11:08 +02:00
Lars-Peter Clausen debca3a153 fmcjesdadc1: vc707: Remove unsed mb_intrs signal
The mb_intrs signal is never driven, it is a leftover of an earlier version
of the file, remove it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:38:25 +02:00
Lars-Peter Clausen 0360e8587e Connect JESD204 interrupts
Connect the ADI JESD204 link layer peripheral interrupt signals in all
projects.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-07-05 14:37:50 +02:00
Rejeesh Kutty 3fb5408acc fmcjesdadc1/a10gx- fix sysref, lvds io and such 2017-06-15 13:57:21 -04:00
Rejeesh Kutty 6ec9eab7b9 fmcjesdadc1/a10soc- fix sysref, lvds io and such 2017-06-15 13:57:21 -04:00
Rejeesh Kutty ef290ef484 hdlmake.pl updates 2017-06-15 11:42:44 -04:00
Rejeesh Kutty e33e6a84f4 a5gt/a5soc - removed 2017-06-15 11:41:28 -04:00
Rejeesh Kutty 7ac083b932 fmcjesdadc1/a10soc- sysref fixes 2017-06-15 10:15:59 -04:00
Rejeesh Kutty 004aee930b fmcjesdadc1/a10gx- fix sysref, gpio connections 2017-06-14 14:40:23 -04:00
Rejeesh Kutty dba419239b hdlmake.pl updates 2017-06-14 10:41:14 -04:00
Rejeesh Kutty 3299d244fe fmcjesdadc1: a10gx/a10soc 2017-06-14 10:39:57 -04:00
Rejeesh Kutty 38c708d4d0 fmcjesdadc1: a10gx/a10soc 2017-06-14 10:39:38 -04:00
Rejeesh Kutty 051c1d6644 fmcjesdadc1: a10soc 2017-06-13 15:00:22 -04:00
Rejeesh Kutty c1bc1259a7 fmcjesdadc1: a10gx 2017-06-13 12:39:45 -04:00
Rejeesh Kutty 3f3ea5f99a hdlmake.pl- updates 2017-06-13 09:55:08 -04:00
Rejeesh Kutty 0eacde9158 fmcjesdadc1/a5soc- alt 16.1 updates 2017-06-13 09:54:01 -04:00
Rejeesh Kutty 6decba3c3b hdlmake.pl updates 2017-06-09 16:23:17 -04:00
Rejeesh Kutty 74f9a99655 fmcjesdadc1/a5gt- altera 16.1 updates 2017-06-09 16:20:49 -04:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 4c998d1e18 make: Update make files 2017-05-25 15:12:17 +03:00
Lars-Peter Clausen d4c9f1e9f1 fmcjesdac1: Convert to ADI JESD204
Convert the FMCJESDADC1 project to the ADI JESD204 link layer core. The
change is very straight forward, but a matching change on the software side
is required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Lars-Peter Clausen 01aea161fa Create CDC helper library
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Rejeesh Kutty ebeebdddf0 altera- infer latest versions 2017-05-12 13:40:14 -04:00
Istvan Csomortani 0442e7d404 util_adxcvr: Fix parameter setup at instantiation
If a parameter value is defined as a string binary (e.g. "001001000000"),
it can confuse the tool, and the value may be used as a decimal number.
To prevent this issue and to improve readability converting all the binary
constants into hexadecimal.
2017-04-27 15:35:39 +03:00
Istvan Csomortani 95249d2165 fmcjesdadc1: Update IP instantiations 2017-04-21 15:08:16 +03:00
Adrian Costina 942d69a30c Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00