4f918cdce9
2014.4.1 ultrascale updates
2015-02-26 16:10:57 -05:00
847c2e049a
kcu105: removed lutram constraints
2015-02-26 16:09:55 -05:00
1613f7fb41
cftl_cip: Add util_pmod_fmeter IP to library
...
Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
abde4048e0
fmcomms1: Add extra AXI slice on ADC DMA path
...
Add a extra AXI slice on the ADC DMA data path to the HP interconnect to
improve the timing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-20 16:43:45 +01:00
b9d16a7eb1
scripts: renaming board parameters
2015-02-20 09:12:30 -05:00
288f5378ff
rfsom: schematic changes
2015-02-18 14:32:41 -05:00
93e2bcd911
rfsom: schematic changes
2015-02-18 14:32:30 -05:00
383cf3b3a3
rfsom: schematic changes
2015-02-18 14:32:20 -05:00
d2e9b1fe03
rfsom: schematic changes
2015-02-18 14:32:04 -05:00
3113abf038
cftl_cip: Add gpio counter for CN0332
...
Add a counter core to the design, to support the CN0332 pmod with a speed sensor.
Change a naming for the custom cores.
2015-02-18 18:24:46 +02:00
e111e1336e
conflicts-
2015-02-06 22:14:21 -05:00
2d607d765b
cftl_cip: Add a clock input to the device core, for the SPI clock.
...
This clock can be adjustable from the system_project.tcl
2015-02-04 14:55:17 +02:00
996e1b7970
rfsom: constraint updates
2015-02-03 14:20:34 -05:00
fd2ab02174
cftl_std: Added in the constraint file comments regarding supported CFTLs
2015-01-29 16:27:43 +02:00
d69d105b5d
vc707_common: Fix address mapping
...
The axi_ethernet/eth_buf/S_AXI_2TEMAC address space and axi_ethernet/eth_mac/s_axi/Reg address
segment does not exist in 2014.4.
2015-01-29 12:22:06 +02:00
e8ff30119d
vc707_xdc: Delete unnecessary clock definition
2015-01-29 11:39:10 +02:00
6c8ea24f20
common: Update VC707 base design to 2014.4
2015-01-28 16:24:52 +02:00
e1d8dd10a9
daq2: Initial check in of the VC707 based project
...
NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.
2015-01-28 16:24:06 +02:00
659e0cca4e
cftl_cip: Initial check in.
...
Project cftl_cip supports the following Circuits from the Lab pmods:
+ EVAL-CN0350-PMDZ
+ EVAL-CN0335-PMDZ
+ EVAL-CN0336-PMDZ
+ EVAL-CN0337-PMDZ
Note: Additional testing needed!
2015-01-23 18:29:32 +02:00
463a3bbc88
cftl_std: Updated project. Switched to PS7 gpio. Renamed signals.
2015-01-23 14:11:33 +02:00
9672271155
fmcjestadc1: a5gt: Updated project to work with linux and fixed ethernet
...
- added phy reset mechanism for proper functioning of the ethernet
- not all DDR is accesible, as NIOS2 can't access it with MMU enabled
2015-01-23 13:30:56 +02:00
5a77ab0161
a5gt:common: Added phy reset signal from ethernet in pin assignments
2015-01-23 12:31:41 +02:00
050f17e034
a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2
2015-01-23 12:30:16 +02:00
72e89852b6
daq2/kc705: 2014.4 updates
2015-01-14 12:58:08 -05:00
024d9e7309
replace export hardware -- hwdef/sysdef
2015-01-13 13:40:21 -05:00
03988f1c9f
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:20 -05:00
b595cce697
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:18 -05:00
b0b4bfe531
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:17 -05:00
47871287f3
kc705: Updated base project with linear flash. Updated all depending projects
2015-01-13 10:19:07 +02:00
b9e2c5659f
fmcomms2: 2014.4
2015-01-09 14:12:54 -05:00
9e64df917c
daq2: 2014.4
2015-01-09 14:12:53 -05:00
65d9f08763
zc706: mig 2014.4
2015-01-09 14:12:52 -05:00
868df1aac8
zc706: mig 2014.4
2015-01-09 14:12:51 -05:00
0258afbadc
board: add ddr seg variable
2015-01-09 14:12:50 -05:00
22d881981e
cftl_std: Renamed cftl standard project
2015-01-09 19:44:13 +02:00
debbe31713
Merge remote-tracking branch 'origin/master' into dev
2015-01-09 11:12:56 -05:00
117686f352
ad9739a: updates for ad9739a
2015-01-09 10:54:50 -05:00
785d3a4ae3
ad9739a: updates for ad9739a
2015-01-09 10:54:40 -05:00
e8d0782a2e
ad9739a: updates for ad9739a
2015-01-09 10:54:22 -05:00
baea2090d6
ad9739a: updates for ad9739a
2015-01-09 10:54:12 -05:00
c9b6411e86
ad9739a: updates for ad9739a
2015-01-09 10:54:00 -05:00
51e6d0888a
cftl_xil_zed: Initial commit for common platform used with CFTL circuits
...
This common platform uses PS7 SPI and I2C to communicate with different chips.
On different connectors different pin configurations are supported:
- On connector JA, a spi interface and a 2 pin GPIO
- On connector JB, a I2C interface
- On connector JC, a spi interface with 2 chip selects
2015-01-09 17:47:29 +02:00
a9cc8f6c91
ad9739a_fmc: added
2015-01-08 10:35:59 -05:00
a170ebfb82
imageon: Initial commit
...
Initial commit of the IMAGEON project for ZC706. NOT tested.
2015-01-08 17:01:22 +02:00
f566268db5
zed_common: Updated common to 2014.4
2015-01-08 11:59:26 +02:00
f6df66ea06
motcon2_fmc: initial commit of the base design
...
Because vivado crashes when adding the speed detector, it's not part of this commit.
The controller is also not part of this commit
2015-01-08 11:57:22 +02:00
eb569b991d
dmafifo- remove util fifo setup
2015-01-06 16:23:14 -05:00
9e707d8a33
rfifo: wrapper updates
2015-01-06 16:17:33 -05:00
a944deebd5
wfifo: wrapper updates
2015-01-06 16:17:25 -05:00
d2baf17ff0
rfsom: updated to rfsom
2014-12-23 14:04:02 -05:00
3d1ba585ee
rfsom: updated to rfsom
2014-12-23 14:04:01 -05:00
19c2da836c
rfsom: updated to rfsom
2014-12-23 14:03:59 -05:00
61ba4f4357
rfsom: updated to rfsom
2014-12-23 14:03:58 -05:00
614dfcd93c
rfsom: updated to rfsom
2014-12-23 14:03:57 -05:00
4b571ded8f
fmcomms2/rfsom: initial commit
2014-12-23 14:03:56 -05:00
ee52602c89
rfsom: initial commit
2014-12-23 14:03:55 -05:00
8e41af7b92
fmcomms2: 2014.4 update
2014-12-23 14:03:54 -05:00
0de1a38245
zc706: 2014.4 update
2014-12-23 14:03:52 -05:00
43037a42eb
scripts: 2014.4 update
2014-12-23 14:03:51 -05:00
71baa129a7
VC707: Fixed linear flash timings
2014-12-19 15:45:14 +02:00
2ff72d60d1
fmcomms2: Updated VC707 project to fix ethernet problem
2014-12-19 15:45:05 +02:00
4a9c4cdf19
fmcadc2_zc706: Fix PLDDR fifo name
2014-12-19 13:01:33 +02:00
6230cb25b7
fmcomms7_zc706: Add constraint file for PLDDR
2014-12-19 13:01:27 +02:00
6e124c4c24
fmcomms7_zc706: Connect PLDDR rst to external push button
2014-12-19 13:01:21 +02:00
a0b83bac7f
fmcomms7_zc706: Delete trailing spaces from system top
2014-12-19 13:01:15 +02:00
362b0f5300
daq3_zc706: Add constraint file for PLDDR
2014-12-19 13:01:10 +02:00
d77e28e372
daq3_zc706: Connect PLDDR rst to external push button
2014-12-19 13:01:05 +02:00
d483801e2d
daq3_zc706: Delete trailing spaces from system_top
2014-12-19 13:00:59 +02:00
df205f5cea
fmcadc2_zc706: Connect PLDDR rst to external push button
2014-12-19 13:00:53 +02:00
8fc1f046a4
fmcadc4_zc706: Add constraint file for PLDDR
2014-12-19 13:00:48 +02:00
7ec1e282d9
daq2_zc706: Add constraint file for the PLDDR
2014-12-19 13:00:42 +02:00
a6cf615ee0
zc706_constr: Move the sys_rst related constraint definition to zc706_system_mig_constr.xdc
2014-12-19 13:00:35 +02:00
153a4cef18
daq2: missing sys_rst decl.
2014-12-19 13:00:21 +02:00
ad144ef06a
plddr3: sys-rst from board pushbutton
2014-12-19 13:00:07 +02:00
33a8c8a155
plddr3: sys-rst from board pushbutton
2014-12-19 13:00:01 +02:00
0cc29fe03b
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:54 +02:00
51bdcb1b12
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:48 +02:00
daba3fb72e
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:42 +02:00
758ac6bb8e
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:35 +02:00
1a9eb8196a
VC707: Fixed linear flash timings
2014-12-18 17:49:00 +02:00
23e2886b5d
fmcadc2_zc706: Fix PLDDR fifo name
2014-12-18 16:57:19 +02:00
b684c8bf33
fmcomms7_zc706: Add constraint file for PLDDR
2014-12-18 10:15:11 +02:00
ae09030044
fmcomms7_zc706: Connect PLDDR rst to external push button
2014-12-18 10:14:32 +02:00
0aa4661122
fmcomms7_zc706: Delete trailing spaces from system top
2014-12-18 10:13:16 +02:00
e81327b794
daq3_zc706: Add constraint file for PLDDR
2014-12-18 10:08:33 +02:00
8121d11993
daq3_zc706: Connect PLDDR rst to external push button
2014-12-18 10:07:52 +02:00
090aed508e
daq3_zc706: Delete trailing spaces from system_top
2014-12-18 10:06:29 +02:00
abdb59a28e
fmcadc2_zc706: Connect PLDDR rst to external push button
2014-12-18 10:04:01 +02:00
31a95042cf
fmcadc4_zc706: Add constraint file for PLDDR
2014-12-18 10:01:16 +02:00
39cc7b8b2e
daq2_zc706: Add constraint file for the PLDDR
2014-12-18 10:00:35 +02:00
59e610be09
zc706_constr: Move the sys_rst related constraint definition to zc706_system_mig_constr.xdc
2014-12-17 19:07:43 +02:00
656246f2ba
fmcomms2: Updated VC707 project to fix ethernet problem
2014-12-17 16:16:01 +02:00
90fe993db2
daq2: missing sys_rst decl.
2014-12-15 14:39:40 -05:00
725b407523
plddr3: sys-rst from board pushbutton
2014-12-15 12:59:36 -05:00
7b1e3d77e8
plddr3: sys-rst from board pushbutton
2014-12-15 12:59:25 -05:00
0a6769fda9
plddr3: sys-rst from board pushbutton
2014-12-15 12:59:16 -05:00
f99bd3609b
plddr3: sys-rst from board pushbutton
2014-12-15 12:59:04 -05:00
77fa96fa67
plddr3: sys-rst from board pushbutton
2014-12-15 12:58:54 -05:00
ed7f8b4908
plddr3: sys-rst from board pushbutton
2014-12-15 12:58:44 -05:00
ca36ef0e02
Merge remote-tracking branch 'origin/hdl_2014_r2' into dev
2014-12-11 11:26:30 -05:00
d82952b22a
daq2/kcu105: lane assignment fixes
2014-12-11 11:19:38 -05:00
7dddac84f1
motcon1_fmc: Fixed issue introduced by merge
2014-12-11 14:32:32 +02:00
9e8fd8ed9e
base_design: External IIC reset is connected to Vcc
...
External IIC reset is connected to Vcc in case of AC701, KC705 and VC707
2014-12-11 11:14:54 +02:00
caa0268434
base_design: External IIC reset is connected to Vcc
...
External IIC reset is connected to Vcc in case of AC701, KC705 and VC707
2014-12-11 11:13:07 +02:00
86ad9213e0
fmcomms2: Update c5soc system_timing script
2014-12-10 17:54:11 +02:00
6ac774a9dd
fmcjesdadc1: Update altera system_timing script
2014-12-10 17:53:29 +02:00
e7c920bbd9
fmcomms2/ml605: compilation fixes
2014-12-09 14:32:39 -05:00
4cf435ee39
fmcomms2/ml605: compilation fixes
2014-12-09 14:32:39 -05:00
8b41034825
fmcomms2/ml605: compilation fixes
2014-12-09 14:32:39 -05:00
842ba19aaa
fmcomms2/ml605: compilation fixes
2014-12-09 14:31:12 -05:00
d7a6b5e6d0
fmcomms2/ml605: compilation fixes
2014-12-09 14:31:11 -05:00
d57b6b01c6
fmcomms2/ml605: compilation fixes
2014-12-09 14:31:10 -05:00
9103f6706e
Merge branch 'hdl_2014_r2' of https://github.com/analogdevicesinc/hdl into hdl_2014_r2
2014-12-09 17:38:37 +01:00
138e789fb6
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl: Fix interrupts
...
sys_concat_intc: don't reset NUM_PORTS to 6
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-09 17:38:16 +01:00
772edbae20
fmcadc4: fifo updates
2014-12-09 10:43:02 -05:00
d149890426
fmcadc4: fifo updates
2014-12-09 10:43:02 -05:00
dad0745fbe
fmcadc4: fifo updates
2014-12-09 10:43:02 -05:00
987257e3c3
fmcadc4: fifo updates
2014-12-09 10:43:01 -05:00
0c6cbdd303
fmcadc4: fifo updates
2014-12-09 10:38:51 -05:00
f044ab94e0
fmcadc4: fifo updates
2014-12-09 10:38:50 -05:00
e2a9502e1e
fmcadc4: fifo updates
2014-12-09 10:38:49 -05:00
a2607a8057
fmcadc4: fifo updates
2014-12-09 10:38:47 -05:00
a6b7b9d880
ad9467_kc705: Fix memory segment offset for SEG_axi_ddr_cntrl
2014-12-09 16:20:39 +02:00
2e4640d5c5
ad9467_kc705: Fix memory segment offset for SEG_axi_ddr_cntrl
2014-12-09 16:17:46 +02:00
4d28825741
ad9467_kc705: Fix typos.
2014-12-09 13:46:51 +02:00
a0d5e7862e
ad9467_kc705: Fix typos.
2014-12-09 12:07:49 +02:00
915ee7a268
fmcjesdadc1_kc705: Connect the SPI interrupt to the controller
2014-12-09 11:54:16 +02:00
ee04eb637b
ad9467_kc705: Fix interrupts
2014-12-09 11:54:08 +02:00
37c3af9929
fmcjesdadc1_kc705: Connect the SPI interrupt to the controller
2014-12-09 11:51:36 +02:00
b83299c606
ad9467_kc705: Fix interrupts
2014-12-09 11:48:46 +02:00
1b4a4bc06e
daq3: compilation fixes - latest changes
2014-12-08 14:51:52 -05:00
c0d588ba8c
daq3: compilation fixes - latest changes
2014-12-08 14:51:52 -05:00
26d72d306e
daq3: compilation fixes - latest changes
2014-12-08 14:51:51 -05:00
abff7097f6
daq3: compilation fixes - latest changes
2014-12-08 14:50:03 -05:00
8a72a6a0dc
daq3: compilation fixes - latest changes
2014-12-08 14:49:52 -05:00
7c3ed75b79
daq3: compilation fixes - latest changes
2014-12-08 14:49:40 -05:00
0a8fabe874
Merge branch 'hdl_2014_r2' into dev
...
Conflicts:
projects/fmcadc5/common/fmcadc5_bd.tcl
projects/motcon1_fmc/common/motcon1_fmc_bd.tcl
projects/motcon1_fmc/zed/system_constr.xdc
projects/motcon1_fmc/zed/system_top.v
2014-12-08 11:32:13 -05:00
82b9ebe23d
remove replaced projects
2014-12-08 10:45:12 -05:00
19e4950b72
renamed to match official names
2014-12-08 10:44:15 -05:00
a558d4000d
motcon1_fmc: Added XADC to the project, the external muxing is controlled by generic GPIO, not XADC GPIO
2014-12-08 11:27:47 +02:00
d5572eaa49
ad9265_fmc: Fix unconnected DMA irq
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-12-05 17:44:47 +01:00
84174460bb
projects/common/kcu105/kcu105_system_bd: Restore axi_ethernet SupportLevel 0
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:50:45 +01:00
bb6cc40902
projects/common: KCU105 VC707 update and sync axi_ethernet:6.1 features
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:50:45 +01:00
8e4d0a1b60
projects/common: KCU105 VC707 KC705 sync microblaze core defaults
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:50:45 +01:00
7e18162632
projects/common/kcu105/kcu105_system_bd: Restore axi_ethernet SupportLevel 0
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:48:37 +01:00
e6e9c0058d
motor_control: Updated project to Vivado 14.2. Temporary removed XADC
...
- fixed constraints
- updated interrupt system
- used ad_iobuf
- The XADC was removed because the XADC IPI generates vaux inputs 0 and 10 even if 0 and 8 are selected
2014-12-05 11:53:23 +02:00
4c05e8de5d
motor_control: Updated project to Vivado 14.2. Temporary removed XADC
...
- fixed constraints
- updated interrupt system
- used ad_iobuf
- The XADC was removed because the XADC IPI generates vaux inputs 0 and 10 even if 0 and 8 are selected
2014-12-05 11:48:00 +02:00
11f41d1dff
zynq_plddr3: Fix PLDDR3's Reset Generator
...
Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset.
Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to
set this two property of the reset generator.
2014-12-04 15:42:28 +02:00
34ffa15b12
zynq_plddr3: Fix PLDDR3's Reset Generator
...
Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset.
Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to
set this two property of the reset generator.
2014-12-04 15:39:17 +02:00
58bc7c6886
fmcomms6: Add DMA overflow signal to ILA
...
This is useful for debugging DMA overflows.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-04 14:23:09 +01:00
a9c6148570
fmcomms6: Better cope with higher sample rates
...
There can be a rather high latency between the last byte of a burst has been send and the time the response for the burst is received. Running at high samplerates this can cause the internal DMA store and forward FIFO to fill up and subsequently stall the DMA pipeline and drop samples. To better cope with the situation double the size of the internal FIFO. Also increase the clock of the AXI bus to be able to accommodate a samplerate of 310MHz.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-04 13:56:59 +01:00
324c0528c2
fmcomms6: Better cope with higher sample rates
...
There can be a rather high latency between the last byte of a burst has been send and the time the response for the burst is received. Running at high samplerates this can cause the internal DMA store and forward FIFO to fill up and subsequently stall the DMA pipeline and drop samples. To better cope with the situation double the size of the internal FIFO. Also increase the clock of the AXI bus to be able to accommodate a samplerate of 310MHz.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-04 13:28:37 +01:00
46156b7ceb
fmcomms6: Add DMA overflow signal to ILA
...
This is useful for debugging DMA overflows.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-04 13:28:37 +01:00
3cc890e604
projects/common: KCU105 VC707 update and sync axi_ethernet:6.1 features
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-04 09:49:09 +01:00
2d8450abc4
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-12-04 09:47:46 +01:00
3bc9b25e96
projects/common: KCU105 VC707 KC705 sync microblaze core defaults
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-04 09:47:02 +01:00
56a8a54080
ad9625x2_fmc: Increase the dma fifo data depth
2014-12-03 12:13:08 +02:00
757c213165
ad9625x2_fmc: Integrate the dac spi interface into the SPI interface
2014-12-03 12:06:43 +02:00
48673fec6a
ad9625x2_fmc: Integrate the dac spi interface into the SPI interface
2014-12-03 12:01:47 +02:00
80d1314c5e
ad9625x2_fmc: Reverse "Add a separate SPI for the DAC interface"
2014-12-03 10:14:09 +02:00
d89ed56e10
ad9625x2_fmc: Increase the data depth of the dmafifo
2014-12-02 19:29:19 +02:00
0007054638
ad9625x2_fmc: Add a separate SPI for the DAC interface
...
DAC spi interface is controlled by an axi_spi core.
Modifications on GPIO layout: pwr_good is 12, vdither 13 and trig is 14.
2014-12-02 19:29:18 +02:00
805d52346c
fmcomms7: compilation fixes on plddr3
2014-12-02 10:39:01 -05:00
f01d1aae2d
fmcomms7: compilation fixes on plddr3
2014-12-02 10:38:44 -05:00
95e113e1a3
fmcomms6: Connect DMA directly to the HP port
...
The axi_dmac supports native AXI3, there is no need to add a interconnect
for protocol conversion between it and the HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:45:45 +01:00
45fc7bb7e2
fmcomms6: Set ila type to native
...
With version 4.0 ila defaults to the AXI monitor type, so explicitly
configure it for native.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:45:45 +01:00
5b68b79dec
ad9467_fmc: Set ila type to native
...
With version 4.0 ila defaults to the AXI monitor type, so explicitly
configure it for native.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:45:45 +01:00
d773673e4f
fmcomms6: Connect DMA directly to the HP port
...
The axi_dmac supports native AXI3, there is no need to add a interconnect
for protocol conversion between it and the HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:44:09 +01:00
5169d3ef59
fmcomms6: Set ila type to native
...
With version 4.0 ila defaults to the AXI monitor type, so explicitly
configure it for native.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:44:09 +01:00
3c85c7e2f8
ad9467_fmc: Set ila type to native
...
With version 4.0 ila defaults to the AXI monitor type, so explicitly
configure it for native.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:44:08 +01:00
7a55db59f6
fmcomms2: Zed, fixed iic multiplexer ad_iobuf connections
2014-11-28 14:19:08 +02:00
d5422c2ecc
fmcomms2: Zed, fixed iic multiplexer ad_iobuf connections
2014-11-28 14:17:09 +02:00
d5a1df2fe6
usdrx1_zc706: Update interrupts.
2014-11-27 14:06:13 +02:00
eed1981ede
usdrx1_fmc: Fix GT lane number definition.
2014-11-27 14:05:54 +02:00
a576f7dc98
ad9671_zc706: Update interrupts
2014-11-27 14:05:43 +02:00
0ccc546aeb
ad9671_fmc: Fix GT lane number definition
2014-11-27 14:05:34 +02:00
ee7d427123
ad9671_fmc: Cosmetic changes
...
Delete trailing whitespaces.
2014-11-27 14:05:24 +02:00
4ea86de4db
usdrx1_zc706: Update interrupts.
2014-11-27 14:03:54 +02:00
d1af4d2951
usdrx1_fmc: Fix GT lane number definition.
2014-11-27 14:03:10 +02:00
82561b48cc
ad9671_zc706: Update interrupts
2014-11-27 14:02:18 +02:00
92f85086e3
ad9671_fmc: Fix GT lane number definition
2014-11-27 14:01:36 +02:00
98e8f21c1d
ad9671_fmc: Cosmetic changes
...
Delete trailing whitespaces.
2014-11-27 14:00:35 +02:00
419d38b9f6
kc705_base: Define sys_addr_mem_seg for dmafifo
2014-11-26 15:38:41 +02:00
6fd2f8c913
daq2_fmc: Update interrupts
...
Update interrupts for ZC706 and KC705 carrier.
2014-11-26 15:38:24 +02:00
bfd89dc9c7
daq2_kc705: Fix constraint file
...
I/O standard for trig_[p/n] is LVDS_25
2014-11-26 15:38:10 +02:00
630f26442a
daq2_kc705: Instantiate dmafifo module
2014-11-26 15:37:57 +02:00
00c7b23b21
daq2_fmc: Cosmetic changes
...
Delete trailing whitespaces, no functional changes.
2014-11-26 15:37:48 +02:00
12f1873e17
kc705_base: Define sys_addr_mem_seg for dmafifo
2014-11-26 15:08:55 +02:00
8dad54b6e3
daq2_fmc: Update interrupts
...
Update interrupts for ZC706 and KC705 carrier.
2014-11-26 13:53:18 +02:00
4b6968c2af
daq2_kc705: Fix constraint file
...
I/O standard for trig_[p/n] is LVDS_25
2014-11-26 13:51:46 +02:00
14193cf4bd
daq2_kc705: Instantiate dmafifo module
2014-11-26 13:50:42 +02:00
f28845cc0d
daq2_fmc: Cosmetic changes
...
Delete trailing whitespaces, no functional changes.
2014-11-26 13:48:48 +02:00
199e86d715
fmcomms2: Added iic_fmc_intr to the zed top file
2014-11-26 11:47:16 +02:00
03751827cb
fmcomms2: Updated vc707 project
...
- updated constraints
- updated interrupts
- used ad_iobuf
- added linear_flash
2014-11-26 11:47:06 +02:00
40c5816bd7
fmcomms2: Updated mitx045 project. Updated constraints. Updated interrupts
2014-11-26 11:46:53 +02:00
84052ad437
Add Vivado version check to adi_project_create
...
The scripts generating the projects files typically only work correctly with
one specific version of Vivado. If a incorrect version is used the script
may fail at some point with a cryptic error message or may not fail but
create a bitstream that is not working as expected, e.g. unconnected
signals, etc. This patch adds a version check to adi_project_create that
will error out early on stating that the wrong version of Vivado was used
and which is the right version to use.
By default the required version will be the version that is required by the
common scripts. Individual projects can overwrite the required version by
setting the REQUIRED_VIVADO_VERSION variable to the required version or can
bypass the version check completely by setting the IGNORE_VERSION_CHECK
variable to 1.
Callers of the script can also disable the version check by setting the
ADI_IGNORE_VERSION_CHECK environment variable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-11-26 10:46:34 +01:00
303a2683a2
fmcomms2: Added iic_fmc_intr to the zed top file
2014-11-26 11:26:58 +02:00
6227bc82c0
fmcomms2: Updated vc707 project
...
- updated constraints
- updated interrupts
- used ad_iobuf
- added linear_flash
2014-11-26 11:25:19 +02:00
2f77daf71d
fmcomms2: Updated mitx045 project. Updated constraints. Updated interrupts
2014-11-26 11:21:20 +02:00
626b719ad8
ad6676ebv_vc707: Update the interrupts
2014-11-26 10:56:47 +02:00
322324b891
ad6676evb_vc707: Add support for linear flash
2014-11-26 10:56:36 +02:00
67f82c9e3e
ad6676_fmc: Fix GT lane number definition
2014-11-26 10:56:23 +02:00
5e70ef4ab9
ad6676ebv_vc707: Update the interrupts
2014-11-26 10:49:14 +02:00
72f9dd226a
ad6676evb_vc707: Add support for linear flash
2014-11-26 10:48:27 +02:00
d75487d0a2
ad6676_fmc: Fix GT lane number definition
2014-11-26 10:45:00 +02:00
81f0e417d4
Add Vivado version check to adi_project_create
...
The scripts generating the projects files typically only work correctly with
one specific version of Vivado. If a incorrect version is used the script
may fail at some point with a cryptic error message or may not fail but
create a bitstream that is not working as expected, e.g. unconnected
signals, etc. This patch adds a version check to adi_project_create that
will error out early on stating that the wrong version of Vivado was used
and which is the right version to use.
By default the required version will be the version that is required by the
common scripts. Individual projects can overwrite the required version by
setting the REQUIRED_VIVADO_VERSION variable to the required version or can
bypass the version check completely by setting the IGNORE_VERSION_CHECK
variable to 1.
Callers of the script can also disable the version check by setting the
ADI_IGNORE_VERSION_CHECK environment variable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-11-25 18:35:11 +01:00
2e72a2cc0c
fmcomms1: Updated VC707 project with latest interrupts and linear flash. Fixed constraints and constraint priority
2014-11-25 15:00:00 +02:00
dbc9da8598
fmcomms1: Updated KC705 project with latest interrupts. Fixed constraints and constraint priority
2014-11-25 14:56:22 +02:00
87324d8a14
fmcomms1: Updated AC701 project with latest interrupts. Fixed constraints and constraint priority
2014-11-25 14:54:01 +02:00
b8ab2ff847
fmcomms1: updated common project
...
- increased the DMA FIFOs to 64
- added axi slices to the source and destination for DMAs
- for microblaze systems, increade the ad9643 dma data width at destination
- removed sys_fmc_dma_clk and used the sys_200m_clk instead for DMA data transfer
2014-11-25 14:51:42 +02:00
2bd154ad59
xfest14_zed: Update project to 2014.2
2014-11-25 12:53:42 +02:00
a1e67a5912
ad9625x2_fmc: dmafifo address width now is an argument of the process
2014-11-24 19:22:18 +02:00
660424ef99
fmcomms6_fmc: Update interrupts
2014-11-24 18:23:35 +02:00
56aefb62ed
fmcomms6_fmc: Cosmetic changes
...
Delete trailing white spaces, and fix alignment.
2014-11-24 18:23:34 +02:00
68ac015825
daq1_fmcl: Fix GT lane number definitions
...
Update which fix issues caused by GT lane number parameters change. (commit f8e7796592
2014-11-24 18:23:33 +02:00
0ecfc14e95
daq1_fmc: Update interrupts.
2014-11-24 18:23:32 +02:00
9b104f1657
daq1_fmc: Get rid of the concat module inside the block design.
...
xl_concat just causing troubles, no need to use it, if not justified.
2014-11-24 18:23:30 +02:00
64b4d0177e
ad9467_zed: Using ad_iobuf module for IO buffer instantiations on top
...
No functional changes, we just try to keep consistency.
2014-11-24 18:23:29 +02:00
83c2eefea2
ad9467_fmc: Update interrupts
2014-11-24 18:23:28 +02:00
114406335d
ad9467_fmc: Connect dma controller directly to the HP port
2014-11-24 18:23:27 +02:00
67065a3130
ad9680_eval: removed
2014-11-24 11:04:34 -05:00
76fb5d3da9
ad9625_vc707: dmafifo address width now is an argument of the process
2014-11-24 16:52:10 +02:00
1834cf6d38
adi_prcfg_project: Update the PR design flow
...
Optimization directive kept on default in the implementation flow.
2014-11-21 19:26:33 +02:00
83d79a6acf
fmcomms2_pr: Update system_project script for mitx
...
Bist logic is using the pnmon module for PRBS checking.
2014-11-21 19:23:12 +02:00
6517a94929
fmcomms2_pr: Update interrupts and iobuf
...
No functional changes, update to the new interrupt path, and change the
iobuf instantiation in order to keep consistency.
2014-11-21 19:22:03 +02:00
65588f1b67
fmcomms2_pr: Cosmetic changes of mitx system top.
2014-11-21 19:20:30 +02:00
84f8377beb
fmcjedadc1_vc707: Add support for linear flash interface
2014-11-21 19:19:21 +02:00
e8546b9c3b
fmcjesdadc1: Update interrupts for KC705 and VC707
2014-11-21 19:18:30 +02:00
b0f571ce0c
fmcjesdadc1: Fix parameter lane number for GT core
2014-11-21 19:17:29 +02:00
c0f4d7e2b5
mitx045_common: Definition file patch
...
In 2014.2 tool version, the way how a definition file needs to be applied is different
The command "apply_bd_automation" should be used, instead setting property PCW_IMPORT_BOARD_PRESET
In non-project mode (PR design flow), after creating the static design the type of the board is set.
NOTE: the definition file for mitx must be installed accordingly in order to get this work
See link: http://zedboard.org/support/documentation/2056
2014-11-21 19:14:37 +02:00
5e08e18022
ad9434_fmc: Update interrupts
2014-11-21 19:06:48 +02:00
db004641d3
kcu105: dmafifo address width change
2014-11-20 09:28:03 -05:00
cdd1408d3c
dmafifo: parameterized address width
2014-11-20 09:28:02 -05:00
2912372d6e
ad9625_fmc: Add support for AD-JESDCLOCK1-EBZ
...
Connect the SPARE_CLOCK_DUT pin to GPIO, this will be used to reset the AD9527.
The SPI interface for the clock chip is already integrated into the design.
2014-11-18 14:11:51 +02:00
bbf1f0c156
adi_project: Add board definition for mitx045
2014-11-18 10:05:57 +02:00
e3378cd6cb
mitx045_board_definition: revert old board definition file
...
Revert commit 4f6aa159b8
2014-11-18 10:05:55 +02:00
6e194dbcc0
adv7511_ac701: Fix project source files definition
2014-11-18 10:05:54 +02:00
766589637e
prcfg_zc706: Update data width and project script
2014-11-18 10:05:53 +02:00
5c7e8eb926
prcfg_setup: Fix data width, delete invalid ILA configurations
2014-11-18 10:05:51 +02:00
bd57c2246e
prcfg: Increase the PR portion area in order to increase the DSP resource.
2014-11-18 10:05:49 +02:00
344f1bb539
adv7511_kc705: Fix project source definition
2014-11-18 10:05:48 +02:00
01b3495a81
fmcomms1: Updated ZC706 project to be compatible with util_wfifo and increased system_constr.xdc priority
2014-11-17 18:33:21 +02:00
20a3f322e7
fmcomms1: Updated zc702 project
...
- fixed timing constraints, increased system_constr.xdc priority
- used ad_iobuf
- updated interrupt system to latest implementation
2014-11-17 18:32:12 +02:00
adcd16d033
fmcomms1: Updated zed project
...
- fixed timing constraints
- used ad_iobuf
- updated interrupt system to latest implementation
2014-11-17 18:31:24 +02:00
5d1a0a14bf
ad9625x2_fmc: dma fifo changes
2014-11-14 16:00:32 -05:00
2eb80715e3
ad9625_fmc: dma fifo changes
2014-11-13 14:13:00 -05:00
eaacd4d49a
adi_project.tcl: Fix message severity (working solution)
...
Need to define the default/initial severity too.
2014-11-13 18:55:43 +02:00
4bcf338e9b
adi_project.tcl : Fix message severity
...
When message severity is set to 'error', need to do it quiet, other way the tool will stop after synthesis, complaining for previous errors.
2014-11-13 16:33:47 +02:00
5baa015246
kc705_base: Delete timing constraints
2014-11-13 16:30:37 +02:00
3915f7d5f4
daq2: kcu105 dma-fifo changes
2014-11-12 15:25:13 -05:00
d79e95b774
daq2: dma-fifo changes
2014-11-12 15:24:54 -05:00
074662a622
dmafifo: common interface with fifo2s
2014-11-12 15:24:31 -05:00
855919ee8e
plddr3: internal buswidth/clock conversion
2014-11-12 14:43:50 -05:00
dbf5acde76
plddr3: internal buswidth/clock conversion
2014-11-12 14:43:49 -05:00
c6af2696b3
plddr3: internal buswidth/clock conversion
2014-11-12 14:43:48 -05:00
ce92d49565
adv7511: Updated VC707 project to include linear flash
2014-11-12 11:46:01 +02:00
897f5e219d
ad9625_zc706: Update GT configuration
2014-11-11 19:25:30 +02:00
776a396141
adi_project.tcl: Add new message severity definition
...
Set "Parameter does not exist!" message severity to error.
2014-11-11 19:20:40 +02:00
8147fa0eb6
fmcomms7: asymmetric no of lanes
2014-11-11 08:54:27 -05:00
439cbecf7c
fmcomms7: asymmetric no of lanes
2014-11-11 08:54:26 -05:00
b96a8d01c3
fmcomms7: asymmetric no of lanes
2014-11-11 08:54:25 -05:00
97fa063341
fmcadc3: Fix pre-processing of ADC data
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-11 11:49:40 +01:00
4ccece5c8d
fmcadc3: Add a chip-select decoder to support up to 7 devices
...
This is required for the fmcadc3 board as it features 7 chips all
connected to the same SPI bus (ad9528, ad9234 x2, ada4961 x4).
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-11 11:49:40 +01:00
05ed98f884
common: Updated common constratins for ac701, kc705, vc707, zc702
2014-11-11 12:35:44 +02:00
c1268f089d
scripts: hp/mem updates
2014-11-10 15:06:20 -05:00
3211964c2e
ad6676evb: added
2014-11-10 13:41:01 -05:00
4c0d053055
fmcomms7: compilation fixes
2014-11-10 13:26:28 -05:00
b85c552e43
fmcomms7: constraint updates
2014-11-10 13:26:27 -05:00
87000d7a23
fmcomms7: board updates
2014-11-10 13:26:26 -05:00
82048866dd
fmcomms7: initial updates
2014-11-10 13:26:25 -05:00
c72a04cecf
fmcomms7: initial updates
2014-11-10 13:26:24 -05:00
4d915d539f
fmcomms7: initial updates
2014-11-10 13:26:23 -05:00
0560bd5f99
fmcomms7: initial updates
2014-11-10 13:26:21 -05:00
cbcdf4a2aa
fmcomms7: initial updates
2014-11-10 13:26:20 -05:00
1edef2b8ff
fmcomms7: initial updates
2014-11-10 13:26:19 -05:00
12896c7624
fmcomms7: daq2 copy
2014-11-10 13:26:18 -05:00
50ce2e30be
daq2: ila changes for kcu105 timing
2014-11-10 10:57:35 -05:00
1d73adcbc4
fmcadc3: zc706: Allow to enable pairs of channels and sign-extend data
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-07 18:09:00 +01:00
c33d3dd0af
fmcadc3: zc706: Connect DMA interrupt line
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-07 18:08:24 +01:00
ad08c62b36
fmcomms2: Updated zc702 project. Updated interrupts. Updated constraints
2014-11-07 14:01:55 +02:00
4e11e39956
fmcomms2: Updated zed project
...
- Updated interrupt system to the latest implementation
- Fixed constraints
2014-11-07 13:59:46 +02:00
962df53946
fmcomms2: Updated kc705 project to vivado 2014.2.
...
- Updated interrupt system to the latest implementation
- Fixed constraints
- Used ad_iobuf
2014-11-07 13:58:40 +02:00
db18ed4af2
fmcomms2: Updated ac701 project to vivado 2014.2.
...
- Updated interrupt system to the latest implementation
- Fixed constraints
- Used ad_iobuf
2014-11-07 13:56:00 +02:00
7e2a9ce569
fmcomms2: Updated base design interrupt system for microblaze
2014-11-07 13:54:43 +02:00
0ade2a5f67
fmcomms5: Updated project to vivado 2014.2. Updated interrupt system. Fixed constraints
2014-11-07 13:45:15 +02:00
2d9a529ab8
kcu105: ddr - 800M
2014-11-06 16:50:37 -05:00
abad8ddc28
ad9625x2: fix ila connection
2014-11-06 14:22:46 -05:00
a2a2552c60
ad9625_vc707: Update project to support linear flash interface
2014-11-06 15:01:58 +02:00
d55ddc4da5
ad9625_vc707: Delete SEG_axi_bram_ctl_mem memory segment
2014-11-06 15:01:12 +02:00
0ffb1095d9
Revert "ad9625_vc707: Fix source file definition"
...
This reverts commit 6c80d88a0c
2014-11-06 14:59:08 +02:00
6b7fccf56b
ad9625_fmc: Preserve the IRQ layout
2014-11-06 12:20:26 +02:00
0425202da5
fmcadc3: compilation fixes
2014-11-05 11:59:10 -05:00
fcd015305c
ad9625x2_fmc: Updated vc707 project to include linear flash
2014-11-05 17:19:35 +02:00
4634a4f868
vc707: Added linear flash to the base design
2014-11-05 17:18:40 +02:00
f1c5173a12
motor_control: Renamed the project to motcon1_fmc
2014-11-05 09:51:18 +02:00
0f1bc27e27
fmcadc3: Connect adc_dwr and dma_ready to ILAs
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-04 18:09:30 +01:00
d7ba7a95a6
fmcadc3: Update to use latest DDR3_fifo IP
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-04 18:09:30 +01:00
6c80d88a0c
ad9625_vc707: Fix source file definition
...
The project using "p_sys_dmafifo" process, from sys_axi_dmafifo.tcl.
2014-11-04 15:21:25 +02:00
80646a641b
ad9625x2_fmc: constraints order changes
2014-11-03 15:02:35 -05:00
56e65f5926
ad9625x2_fmc: add dma fifo
2014-11-03 15:02:00 -05:00
8c0782cb74
ad9625x2_fmc: constraints changes
2014-11-03 15:01:40 -05:00
beee377fb7
ad9625x2_fmc: interrupts fix
2014-11-03 15:01:15 -05:00
8e6cb2bad4
ad9625x2_fmc: dma fifo additions
2014-11-03 15:00:51 -05:00
7ad9340992
pmod_ad7175: Connect gain control pin
...
Connect the gain control pin to GPIO32 of the ZYNQ.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-11-03 15:00:02 +01:00
4eea04cc9d
fmcadc3: zc706: Fix DMA enable connection
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-03 14:45:16 +01:00
57137df018
fmcjesdadc1_zc706: Interrupt update
2014-11-03 13:02:09 +02:00
4f815b99a1
kc705_base: Fix sys_concat_intc input connections
...
All the unused input pins need to be connected to ground.
2014-11-03 13:02:08 +02:00
8ef3eada7d
adv7511_ac701: Interrupt update
2014-11-03 13:02:07 +02:00
98b92c4bc1
adv7511_kc705: Interrupt update
2014-11-03 13:02:06 +02:00
0246a40e28
adv7511_vc707: Interrupt update
2014-11-03 13:02:05 +02:00
f7588131da
ac701_base: Interrupt update
2014-11-03 13:02:04 +02:00
b92636c6eb
kc705_base: Interrupt update
2014-11-03 13:02:03 +02:00
25f37ffce7
usdrx1: Added cpld configuration files
2014-11-03 12:54:54 +02:00
99ad286c41
kcu105: adv7511 updates
2014-10-31 13:28:17 -04:00
8ed9d10502
ad9625_fmc: disable sync
2014-10-31 13:05:18 -04:00
6f5a268909
fmcomms1: ZC706, updated project with latest constraints and interrupts
2014-10-31 17:59:56 +02:00
a84397d345
motor_control: Changed the encoder pins mapping.
2014-10-31 17:37:28 +02:00
356e1c7ac1
motor_control: Changed the encoder pins mapping.
2014-10-31 17:08:18 +02:00
3c78d8fe58
ad9265_fmc: Added correct fifo to ILA. Updated interrupts
2014-10-31 14:49:29 +02:00
6fac294b6f
fmcomms2: Updated zc706 project to new interrupt system
2014-10-31 14:15:29 +02:00
91ea11041d
prcfg_mitx045: Upgrade of the project script.
...
- the design using the common PN monitor
- the first implemented logic will be the qpsk, to get a better result
- cosmetic changes
2014-10-31 12:18:00 +02:00
e450e78f13
prcfg: Update design to Vivado 2014.2
2014-10-31 12:05:19 +02:00
860a7caa56
prcfg: dac and adc to dma interface width is 64
2014-10-31 12:04:34 +02:00
ea194755e1
prcfg: Upgrade the QPSK logic
...
Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
2014-10-31 11:59:29 +02:00
16cdae3001
mitx045_base: Delete unnecessary timing constraints.
2014-10-31 11:50:49 +02:00
07673b673a
adv7511_mitx045: Interrupt update
2014-10-31 11:46:27 +02:00
67bec719f7
mitx045_base: Interrupt update
2014-10-31 11:45:33 +02:00
b9f800ff65
fmcadc3: zc706: Fix connection to the system clock
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-10-31 11:06:16 +01:00
21f99b1c97
daq2: remove ila for kcu105
2014-10-30 15:26:29 -04:00
56859ad4c9
sys_dmafifo: use internal memory
2014-10-30 15:26:28 -04:00
5bd00df33a
adv7511_zc706: Interrupt update
2014-10-30 19:02:16 +02:00
d81484a6f3
adv7511_zed: Interrupt update
2014-10-30 19:01:17 +02:00
7ae003cf82
zed_base: Interrupt update
2014-10-30 19:00:05 +02:00
e0b7ef2f4f
scripts: Update scripts for PR design flow
...
+ Rewrite the pr_verify process, to improve verification time
+ Update the implementation flow: always the biggest logic will be implemented first, to achieve a better result
therefore force the tool to optimize the first logic with 'ExploreSequentialArea'
+ Make utilization report just from the PR pblock, that's more relevant as the utilization report of the whole fabric
2014-10-30 18:51:13 +02:00
02b32abefe
adv7511_zc702: Interrupt update
2014-10-30 18:42:14 +02:00
ba53e156e3
ZC702_base: Interrupt update
2014-10-30 18:39:49 +02:00
f595b86576
kcu105: lutram constraints for ies
2014-10-30 11:20:27 -04:00
d0a70380bf
kcu105: lutram constraints for ies
2014-10-30 11:19:55 -04:00
4c0e4d280f
dmafifo: internal version- light duty
2014-10-30 11:12:13 -04:00
360e7104b6
dmafifo: axi version- heavy duty
2014-10-30 11:12:12 -04:00
cfa1a93441
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-30 08:42:09 +01:00
56374cf592
usdrx1: Added synchronization, updated constraints, added timing check for a5gt project
2014-10-29 19:29:42 +02:00
cc265b6b9c
daq2/daq3/ad9625_fmc: Connect ADC DMA xfer_req signal
...
For proper operation the xfer_req signal needs to be connected from the ADC DMA to the DDR FIFO.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-29 18:15:54 +01:00
8c789104a6
ad9671: Fixed constraints. Modified system_timing.tcl so that it will fail if timing are not met
2014-10-29 18:25:56 +02:00
2e01ad2eec
ad9625_fmc/zc706: ps7 interrupt updates
2014-10-29 12:13:44 -04:00
b7946febfa
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-29 08:50:51 +01:00
f83622a2e6
daq2/kcu105: interrupt updates
2014-10-28 15:51:42 -04:00
4788d09620
vc707: interrupt updates
2014-10-28 15:42:55 -04:00
c9691fac64
ad9625_fmc: merge zc706 and vc707
2014-10-28 10:12:19 -04:00
627da6161b
ad9625_fmc: remove dma clock for now - zynq/non-zynq merge
2014-10-28 10:12:18 -04:00
36c7034bd6
ad7175: Fix dma issues
2014-10-28 16:00:06 +02:00
9e1d1c1b49
ad7175: Updated the AD7175 IP and project
2014-10-28 14:28:38 +02:00
fd66affa42
scripts: add default memory interconnect
2014-10-27 15:53:20 -04:00
fc4e002150
scripts: add mb cpu side
2014-10-27 15:53:19 -04:00
4f15f5c34c
adv7511: Update interrupts.
...
The ad_interrupts.v was used to concatenate the interrupts.
2014-10-27 19:48:05 +02:00
a870603db5
common_bd: Update the common block designs to the new IRQ path
...
Avoid the use of xil_concat module by using the ad_interrupts.
2014-10-27 19:44:25 +02:00
d04a545a41
fmcomms2: updated zc706 project with new constraint style
2014-10-27 19:27:36 +02:00
61c769e035
kc705: daq2 updates
2014-10-27 09:59:57 -04:00
d1e3993bd0
kcu105: daq2 updates
2014-10-27 09:59:56 -04:00
d471b61f3e
fifo: merge zynq and non-zynq
2014-10-27 09:59:54 -04:00
8b4d70eac6
daq2: merge zc706 and kcu105
2014-10-27 09:59:53 -04:00
54f341fad8
scripts: sdk export before timing check
2014-10-27 09:59:52 -04:00
4494998940
scripts: ignore another variant of reset warning
2014-10-27 09:59:51 -04:00
10b898a62d
zed_base: Fix IRQ layout.
...
Just a temporally fix of IRQ layout.
2014-10-27 14:46:26 +02:00
3645139e59
fmcomms6: Avoiding redefinition of system clocks.
2014-10-23 12:55:56 +03:00
dd5d57843d
fmcomms6: Update version of the ILA core
2014-10-23 12:30:55 +03:00
3dbfa8cda6
ad9434_fmc: Fix PN monitor and device interrupt
2014-10-23 11:29:14 +03:00
24e11b30b9
ad7175_zed: added the ad7175 ZED project
2014-10-23 06:15:17 +03:00
20d59ce39b
daq2: dma fifo modifications
2014-10-22 16:39:28 -04:00
4eeb50114f
daq2: rebase conflicts
2014-10-22 16:39:17 -04:00
43cdafe1e2
kcu105: iic-rstn removed
2014-10-22 16:33:52 -04:00
43fe20d141
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-22 17:19:37 +02:00
dcdba475f7
vc707_common: Fix net name sys_100m_resetn
2014-10-22 15:41:36 +03:00
a0d27a117c
usdrx1: Updated project with new synchronization mechanism. Fixed timing constraints
2014-10-22 13:20:44 +03:00
cd9033296c
ad9671_fmc: Fixed constraint files
2014-10-22 13:14:59 +03:00
17675863e0
all_projects: Fix the interrupt connections to preserve IRQ layout
2014-10-22 11:48:08 +03:00
767179dce9
adv7511_zc706: Fix IRQ layout
...
Fix IRQ connection, this layout works on Linux
2014-10-21 17:44:28 +03:00
2beaeb9176
projects/daq2/kcu105/system_constr.xdc: temp constrains
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-21 15:03:55 +02:00
8a4ab4e05a
projects/ad9434_fmc/common/ad9434_bd.tcl: Fix freeze - Design doesn't use SYNC
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-21 15:03:55 +02:00
d4a21d9775
ad9625_fmc: constraints fix
2014-10-20 10:00:39 -04:00
b3c784f76a
ad9467_fmc: Made some cosmetic changes on the block design script.
2014-10-20 13:28:34 +03:00
4b8720b551
fmcomms2_zc706: Remove top level constraints
...
Remove all the unnecessary top level constraint definitions.
2014-10-20 13:25:01 +03:00
7115864b4c
ad9434_fmc: Remove top level constraints
...
Remove all the unnecessary top level constraint definitions.
2014-10-20 13:23:37 +03:00
5deffd57b1
zed: Remove top level constraints
...
Remove top level constraints from the ZED base design.
2014-10-20 13:20:27 +03:00
0c56e5b912
ad9434_fmc: Fix GPIO width
...
GPIO port width is 15 instead of 32
2014-10-20 10:59:30 +03:00
7f8270d74b
ad9625_fmc: generic dma fifo for zynq and non-zynq boards
2014-10-17 14:38:16 -04:00
0b30f98640
ad9625_fmc/zc706: remove top level constraints
2014-10-17 14:38:15 -04:00
f3c9627cae
adi_project: demote reset warnings to info
2014-10-17 14:38:13 -04:00
14ccdaaa78
kcu105: removed spdif reset
2014-10-17 14:00:00 -04:00
380eeec013
daq2/kcu105: ethernet fix
2014-10-17 13:48:35 -04:00
fca0714478
adv7511/kcu105: ethernet fix
2014-10-17 13:48:33 -04:00
e73b3b52dc
kcu105: ethernet fix
2014-10-17 13:47:50 -04:00
2600b1f359
daq3: tx interleave and dma fifo axi streaming
2014-10-15 14:51:04 -04:00
6d76e0b768
zc706: remove top level constraints
2014-10-15 14:51:02 -04:00
5715c5b28f
dmafifo: axi stream interface
2014-10-15 14:50:57 -04:00
0aed11fa6c
adi_project: demote useless warnings
2014-10-15 14:50:54 -04:00
4d4a7981f2
fmcomms1: Connect DMA controller directly to the HP ports
...
The AXI DMAC controller nativly supports AXI3, there is no need to insert a interconnect to do protocol conversion.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:46:07 +03:00
7d3be14ab5
common: Connect audio clkgen reset
...
While we are at it also hide the unused locked pin.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:44:46 +03:00
fd89458708
common: Set cpu interconnect strategy to minimize area
...
There will rarely be concurrent access to the peripheral control bus
interconnect, so there is no need to optimize for performace. Setting the
interconnect strategy to minimize area can reduce the resource usage by
~90%.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:43:54 +03:00
d2a04856a9
common: Fix xlconstant output pin name
...
On 2014.2 xlconstant output pin name is 'dout'.
2014-10-15 15:37:06 +03:00
02802644bf
fmcjesdadc1: Fix a few warning and issue with ILA
...
+ GPIO width is 15
+ Fix ILA core
2014-10-15 15:37:05 +03:00
865cbab3a2
ad9671_fmc: Updated a5gt project with start of frame information
2014-10-15 10:53:33 +03:00
8934a66013
usdrx1: Update project so that the AD9671 cores can be synchronized
2014-10-13 17:06:40 +03:00
f528873fa9
fmcomms2: Add an additional SPI interface for up/down converter board
...
Supported carriers are: ZC706, ZC702 and Zed.
2014-10-10 18:47:07 +03:00
ca4c961891
fmcomms2: Use ad_iobuf instance on system_top
...
Use ad_iobuf instance on system top, instead of separate IOBUF instances.
2014-10-10 18:45:39 +03:00
e21d26e456
fmcomms2: Cosmetic changes
...
Get rid of unwanted whitespaces.
2014-10-10 18:25:17 +03:00
fe8a076b2e
fmcomms2: Cosmetic changes on *_bd.tcl script
2014-10-10 17:06:32 +03:00
7a9e694446
fmcomms2: Connect DMA directly to the HP ports
...
The DMA controller is able to send AXI3 compatible requests, no need to add
a interconnect for protocol conversion in between the DMA controller and the
HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:14 +03:00
87047fd83e
fmcomms2: Set dac_unpack channels to 4
...
There are only 4 DAC channels in the fmcomms2 design, so set the number of
channels of the dac_unpack core to 4. This slightly reduces resource usage
as well as reducing the DMA alignment requirement from 128bit to 64bit. The
later value is what existing applications expect the alignement requirement
to be.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:06 +03:00
43e9b0c7a6
common: Disable TTC0 MMIO routing for PS7
...
We do not use the ttc0 to MMIO routing, but it is enabled by default, so
explicitly disable it.
2014-10-10 16:19:51 +03:00
e361bbbd04
Revert "fmcomms2_udc: Initial check in"
...
This reverts commit ddc7c845e9
2014-10-10 14:48:55 +03:00
7659f3438c
AD9467: Fixup swapped net names
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-10-10 12:33:07 +03:00
adf4893a27
usdrx1: remove constraints and other changes
2014-10-09 15:25:08 -04:00
ddc7c845e9
fmcomms2_udc: Initial check in
...
FMCOMMS2 with an additional SPI port for the up/down converter board
2014-10-09 19:01:22 +03:00
6f77af4aff
fmcjesdadc1: Upgrade project to 2014.2
2014-10-09 18:55:27 +03:00
2da395926e
fmcomms2: Upgrade project to 2014.2
2014-10-09 18:54:33 +03:00
4f6aa159b8
mitx045: Base design now support 2014.2
2014-10-09 15:11:28 +03:00
edeeafa47d
ad9671_fmc: Added sof information to the AD9671 driver
2014-10-09 14:52:25 +03:00
072e11c661
ad9467_fmc: Upgrade the axi_quad_spi core
2014-10-08 15:22:58 +03:00
fc38249150
ad9467 ZED: Fix over range signal path, and the dma interface.
2014-10-08 11:24:44 +03:00
15db557bd6
ad9467 ZED: Cosmetic changes on bd script.
2014-10-08 11:24:32 +03:00
82717b354a
ad9467_fmc : Upgrade project to 2014.2
2014-10-08 11:21:43 +03:00
b2d0260130
ad9467_fmc: Prevent to use concatenation module on SPI interface
...
This module cause unnecessary issues during version upgrades.
2014-10-08 11:20:45 +03:00
27153fff41
ad9625x2_fmc: updated to 2014.2
2014-10-07 16:05:09 -04:00
2dfcb0c599
usdrx1: Initial commit for a5gt
...
axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
95842b8949
ad9434_fmc: Fix adc_valid signal path
2014-10-07 18:02:33 +03:00
115f33b8d6
ad9434_fmc: Fix pin constraints for ZC706
2014-10-07 17:58:29 +03:00
c1213ffe71
ad9434_fmc: Fix SPI interface
2014-10-07 17:51:14 +03:00
cd42345324
projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-07 09:17:24 +02:00
bca8ec0160
daq2: 2014.2 and ver.d
2014-10-06 14:56:01 -04:00
c375b5b26e
daq3: vivado build
2014-10-06 10:34:02 -04:00
525373fc04
daq3: daq2 copy
2014-10-06 10:34:00 -04:00
210da4116f
scripts: initial commit
2014-10-03 16:13:34 -04:00
f0927afd0b
ad9625_fmc: add dma fifo for non-zynq
2014-10-01 14:51:14 -04:00
89964be59e
fmcomms1: Updated project to vivado 2014.2
2014-09-30 10:32:18 +03:00
041d8faaf7
common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2
2014-09-30 10:31:00 +03:00
922bc6f03a
fmcadc3: 16bit - but ignored 4 lsb(s)
2014-09-29 15:26:30 -04:00
3c25c1171d
fmcomms1: Fixed missing sample issue on ZC706. Added modifications for all other platforms
2014-09-26 10:28:07 -04:00
87c4c73e22
ad9434: Fix adc_clk constraint
...
ADC clock is 500 Mhz.
2014-09-25 16:54:06 +03:00
82ed885b53
ad9434: Fix SPI line physical constraints
...
SPI lines are not differential.
2014-09-25 16:53:16 +03:00
ccb0b135ca
ad9434: Fix the adc to dma interface.
...
All the device2dma interfaces needs to have a generic form : (data, enable, valid)/channel
2014-09-25 16:50:09 +03:00
683561b67d
AD9434: Initial check in of the library and project with ZC706
2014-09-24 18:27:17 +03:00
1d4bc47cea
ad9265: Initial commit
2014-09-23 22:51:42 -04:00
296983707b
usdrx1: Updated project to 2014.2
2014-09-23 22:45:50 -04:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
bdf01738a1
ultrasound: disconnected ADN4670 chips from SPI lines.
...
Connected everything to ground so that the the clock selected is 0 and all outputs are enabled
2014-09-23 22:30:42 -04:00
7e40f99fe9
fmcomms2: Improved constraints for ac701 and zc702. Fixed common design so that ILA works correctly on microblaze based systems
2014-09-23 22:28:27 -04:00
577441bd0c
daq1: clean up dma interfaces
2014-09-23 14:23:41 -04:00
7c98a783c5
2014.2 updates
2014-09-23 12:32:33 -04:00
1682d9da10
fmcadc3: initial updates
2014-09-22 11:27:17 -04:00
5e3076d770
fmcadc3: daq2 copy
2014-09-22 11:27:16 -04:00
dd7bac41c1
daq1 : Update project to 2014.2
...
- Cores are upadted
- Concat module does not swap output anymore
- Clock signal name ps7_clk_* changed to clk_fpga_*
2014-09-22 17:33:50 +03:00
f2cd7626f5
adi_project : ZC706 board name changed on 2014.2
2014-09-22 17:33:49 +03:00
fb5d212370
daq2/kcu105: fixed timing violations
2014-09-19 15:55:42 -04:00
751bdd6cfc
daq1: Update the constraint file
...
- tx_ref_clk and rx_sysref need to be differential
- cosmetic changes
2014-09-19 18:22:57 +03:00
f43b5d707e
fmcomms2: Reduced clock frequency for ILA to meet timing for ZED
...
Modified ZED constraints to 250 MHz for the clock from AD9361
2014-09-16 16:08:28 -04:00
d33fb07587
usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32.
...
GPIOs for which the directions is known, have been specifically assigned.
The SPI clock has been changed to a lower frequency.
2014-09-16 15:56:19 -04:00
d4db53c3b0
usdrx1_spi: Modified module to be compatible with altera
2014-09-16 15:53:11 -04:00
a3dbd5ac00
projects/common/vc707/vc707_system_bd: AD9625_FMC update to 2014.2
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-09-16 14:59:36 +02:00
a91f4bb6b9
daq1: General updates
...
- Add additional GT setups
- Use channel PLL instead of quad PLL
- Add additional ILA probes for debug
2014-09-13 00:23:11 +03:00
d8651cdd2e
fmcomms2: c5soc: Set dac_util_unpack number of channels to 4
...
We only do have 4 channels in this design. Reducing the number of supported
channels for the dac_util_unpack core to 4 from 8 lowers the DMA alignment
requirement from 128bit to 64bit. We need this since applications only
expect a DMA alignment requirement of 64bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:15:12 +02:00
ecc498313c
fmcomms2: c5soc: Connect ADC, DAC and VGA DMA to different bridge interconnects
...
We have enough bridge interconnect to give each DMA its own, so use them.
This makes sure that they do not interfere with each others transfers to
much. The SDRAM controller side of the FPGA2SDRAM bridges FIFO runs at a
much faster frequency then what we are able to use in the fabric. So its
better to do the arbitration on that side of the bus to make sure that we
can utilize the buses in the FPGA fabric to the maximum for each DMA core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:14:07 +02:00
61f21a17b3
fmcomms2:c5soc project upgraded with util_dac_unpack
2014-09-11 15:13:09 -04:00
4c1c50788e
fmcomms5: c5soc: Fix typo
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 17:15:10 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
...
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
647a26e19c
projects/common/vc707/vc707_system_bd.tcl: Select Linux MMU settings
2014-09-10 17:40:36 +02:00
c7989925c5
fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock
...
Otherwise we get timing errors for the reset signal that is generated in the
50MHz clock domain, but used in the VGA PLL clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
328205c31d
fmcomms2: c5soc: Set DMA transfer length to 24 bits
...
14 bits is a bit to low and we use 24 bits everywhere else as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
b58e425b44
daq2/kcu105: timing improvement -register slices hang
2014-09-08 10:24:56 -04:00
6e389b8c47
motor_control: Updated the FOC IP and the encoder connections to the IP
2014-09-06 15:58:03 +03:00
669462e0f6
ad9625x2: updates on pcores
2014-09-05 12:25:43 -04:00
72f31370ef
a5gt: ethernet-fpga lvds mode
2014-09-04 11:19:25 -04:00
3deb55bb98
a5gt: ethernet i/o changed to lvds
2014-09-04 11:19:24 -04:00
dfb94f7b68
motor_control: Modified foc_controller to be compatible with other cores
2014-09-03 12:09:37 +03:00
9f3461b130
fmcjesdadc1: Added support for KC705
2014-09-02 18:02:25 +03:00
17122661d2
fmcomms2_pr: Fix file path on ZC706/system_bd.tcl
2014-09-01 18:49:55 +03:00
2ce7695bf7
fmcjesdadc1: Initial commit of VC707 version
2014-09-01 18:47:01 +03:00
9a80fec4e4
fmcjesdadc1: Delete trailing whitespaces
2014-09-01 18:45:20 +03:00
d08d0cd70b
motor_control: added the MW FOC IP and updated the design
2014-09-01 18:35:21 +03:00
ee752ec08a
daq1: Initial commit
2014-09-01 18:34:31 +03:00
a773cc4992
usdrx1: updated project
...
ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
95c143412d
fmcomms2: Modified design to work with 4 channel util_adc_pack
2014-08-29 13:53:59 +03:00
da913864c9
ad9671_fmc: updates to match recent core changes
2014-08-28 13:16:52 -04:00
5a42c10233
projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI.
2014-08-27 21:46:23 +03:00
c435edf194
ad9652/zc706: fix dma write
2014-08-27 10:44:39 -04:00
7b280b3bbf
fmcomms6: zc706 build-only version
2014-08-27 10:44:37 -04:00
0e909647b4
fmcomms6: initial checkin
2014-08-27 10:44:36 -04:00
a49eb5853b
ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems
...
For ZC706 Fixed one constraint which was not correct
2014-08-26 16:28:41 +03:00
5f21f54463
fmcjesdadc1: zc706 version
2014-08-25 14:28:57 -04:00
cb29b83b05
a5gt: updates to match a5gt
2014-08-25 10:46:59 -04:00
76ffb939e5
zc706: ad9625 copy
2014-08-22 11:24:24 -04:00
fe1eaefcff
fmcomms1: zc706
2014-08-22 09:08:55 -04:00
280260e54c
c5soc: dmac separated slave and master id widths
2014-08-22 09:08:54 -04:00
f3f8414d81
kcu105: changes for ad_iobuf
2014-08-15 15:01:52 -04:00
b481df0b5f
library: local constraints async groups
2014-08-14 15:09:51 -04:00
39bb7ca231
a5soc: fmcjesdadc1+hdmi version
2014-08-14 09:05:38 -04:00
a54e4edb08
Add xfest14 PMODs project
...
This project has a SPI controller connected to each of the ZED boards PMOD
ports JA, JB, JC, JD pin 1-4. Pin 7-10 are connected to the PS7 general purpose
GPIOs, except for JC where it is connected to the PS7 UART controller.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-08-12 10:14:16 +02:00
96969079ce
a5soc: fixes for 14.0 and spi conflicts
2014-08-11 16:46:37 -04:00
902d5b0da2
prcfg: Update fmcomms2_pr for ZC706
2014-08-05 17:55:31 +03:00
Rejeesh Kutty
Istvan Csomortani
Lars-Peter Clausen
Adrian Costina
Michael Hennerich
Paul Cercueil
acozma
dbogdan