c8d3c04a05
ad9625: delay changes
2015-05-19 12:53:56 -04:00
f53204f9f9
ad9467: delay changes
2015-05-19 12:53:56 -04:00
fe0ceb2530
delay-cntrl updates
2015-05-18 15:23:10 -04:00
304a202d67
delay-cntrl updates
2015-05-18 14:57:05 -04:00
2e257db109
delay-cntrl updates
2015-05-18 14:53:24 -04:00
0877c252ad
delay-cntrl changes
2015-05-18 14:28:20 -04:00
2bad47cf4f
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
6e047f78c6
delay-cntrl: up-clk, direct access + tx
2015-05-18 14:28:20 -04:00
2c1719095d
util_axis_resize: Changed _ip.tcl format to the standard format
2015-05-18 17:25:07 +03:00
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
...
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
a07d11c3e9
axi_ad9361_tdd: Define control bits for continuous receive/transmit
2015-05-14 17:21:32 +03:00
c9c05e21c2
axi_dmac: Updated constraints to cover cases when the hierarchy is rebuilt by synthesis
2015-05-13 16:34:06 +03:00
7c9bc40c75
axi_ad9361&TDD: Update TDD
...
+ Delete unnecessary registers
+ Add the module ad_addsub.v to resolve additions and subtractions inside TDD control
+ Redefine the burst logic
+ Redesign the control signal generations
+ Note: This patch fix the TDD related timing violations
2015-05-13 14:03:01 +03:00
a1d680ee6b
ad9680- add hw tcl
2015-05-12 15:06:42 -04:00
833a3de6b5
ad9680- add hw tcl
2015-05-12 15:06:39 -04:00
48c769d431
ad9144- add hw tcl
2015-05-12 14:40:38 -04:00
553f89f59d
ad9144- add hw tcl
2015-05-12 14:39:57 -04:00
4553de3ffa
ad9361- align hold
2015-05-11 11:55:01 -04:00
9934cce5d2
util_dacfifo: Add CDC logic for dma_lastaddr register.
2015-05-11 12:20:46 +03:00
2e7135c3c2
axi_ad9361_tdd: Initial commit.
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Add the TDD register map and TDD control module. Add TDD integration changes to axi_ad9361 IP core.
2015-05-11 12:20:44 +03:00
14e23b106c
axi_ad9361: changed device interface module for Altera to have the same inputs as the one for Xilinx
2015-05-08 17:43:10 +03:00
12ed393d39
ad9361- framing modifications
2015-05-07 15:13:18 -04:00
a68539edf1
ad9361- framing modifications
2015-05-07 15:13:17 -04:00
176a4a4b76
ad9361: add ddr-edgesel
2015-05-06 16:58:50 -04:00
a8534a9c02
ad9361: add ddr-edgesel
2015-05-06 16:58:49 -04:00
32f7e98afd
ad9361: add ddr-edgesel
2015-05-06 16:58:47 -04:00
670850183b
axi_hdmi_tx: Updated constraints as in fmcomms2/zc702 project they were not correctly applied
2015-05-06 18:53:19 +03:00
a7c96fdac8
util_dacfifo: General clean up of the IO, input/output data has the same width
2015-05-06 16:32:44 +03:00
0613dca0b7
axi_dmac: Move the 'axis_xlast' logic into the dest_axi_stream module
2015-05-06 16:10:28 +03:00
949abcdc8f
Makefile: Updated makefiles so that the project recipe does not depend on lib
2015-05-06 14:58:29 +03:00
65af205d6b
axi_dmac: Add axis_last control signal to the Master AXI Streaming interface
...
This control signal can be overwritten by the up_axis_xlast/up_axis_xlast_en bits, in order to create a single stream, which is contains multiple streams.
This can be use to fill up the DACFIFO module.
2015-05-06 13:54:31 +03:00
233cc111d2
util_pmod_adc: Used generated clock for the ADC SPI. Works by default at 6.25MHz
2015-05-05 23:33:13 +03:00
3517b6941c
adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale
2015-05-05 10:06:26 +03:00
707b285669
prcfg: bb def
2015-05-04 10:24:13 -04:00
be32715ab3
axi_adcfifo: Updated constraints
2015-04-30 14:23:24 +03:00
d623f77453
axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
...
Resets for both up clock domain and rx clock domain are needed in some projects
2015-04-30 12:07:36 +03:00
463c4d4d28
util_wfifo: Added constraint for the resetn path
2015-04-30 12:05:02 +03:00
392ba31a07
axi_hdmi_rx: Updated constraints
2015-04-30 12:04:15 +03:00
288b9cccff
Makefile: Added makefiles for imageon_loopback project. Updated axi_ad9152, util_gmii_to_rgmii, util_wfifo to include constraints file
2015-04-28 15:22:37 +03:00
a7a2d194e9
axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core
2015-04-28 15:04:18 +03:00
c36186f75a
axi_ad9643: Added adc_rst output
2015-04-28 14:52:24 +03:00
8ee3f64a65
axi_ad9265: Added adc_rst output
2015-04-28 14:51:14 +03:00
67c581cef8
util_wfifo: Updated to be used with adc_rst from the adc_clk clock domain
2015-04-28 14:50:00 +03:00
1ad87aa27c
util_wfifo: Added constraints
2015-04-27 11:19:56 +03:00
81d4e1d9b1
axi_clkgen: Updated constraints
2015-04-27 11:19:15 +03:00
d950f5ffcd
axi_ad9122: Updated constraints
2015-04-27 11:18:52 +03:00
9fba4cb2ef
util_dacfifo: Add support for Slave AXI stream interface.
...
The FIFO can be initialized through an AXI stream interface too.
2015-04-27 10:40:55 +03:00
3a02998e9a
axi_ad9152/axi_ad9152_ip.tcl: Fix typo
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axi_ad9152_constr.v -> axi_ad9152_constr.xdc
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-24 09:41:43 +02:00
a9924e6401
util_gmii_to_rgmii: Added constraints
2015-04-23 16:53:57 +03:00
bd06bae8c2
library: Modified the adi_ip.tcl script
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The constraints processing order changed to "late" instead of "early", in order for all the clocks in the system to be already created when the IP constraints are applied
2015-04-23 14:31:23 +03:00
Rejeesh Kutty
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen