83399ef6ee
a10gx: Updated common project to work with Linux (enabled MMU)
2015-11-04 13:35:52 +02:00
27266c59ee
ad7616_sdz: Add project source files
2015-11-03 15:03:35 +02:00
a0039ed4fe
ccfmc: Launch HDMI data on falling edge
...
The ADV7511 captures data on the rising edge, so make sure to launch data
on the falling edge. This fixes some issues with image stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-11-03 10:59:13 +01:00
6dddac5d94
ccfmc- missing board io
2015-11-02 15:45:14 -05:00
cafc80c829
fmcadc5: add programmable io delay
2015-11-02 12:10:18 -05:00
8b95520767
pzsdr/ccfmc- add loopback gpio/gt cores
2015-10-30 18:48:26 -04:00
92b7570864
pzsdr/ccfmc- add ad9517 signals
2015-10-30 10:50:53 -04:00
b3cb84cf91
fmcadc5- added ila
2015-10-29 16:48:21 -04:00
24d76c610a
fmcadc5- fix core connections
2015-10-29 16:47:56 -04:00
ac4091e19e
fmcadc4- add monitor fifo
2015-10-27 14:52:02 -04:00
b5d3d0bd13
usb_fx3: Added axi_usb_fx3 core and DMA to the project
2015-10-27 09:41:18 +02:00
748a2bc87a
fmcadc4- add ila for zc706 only
2015-10-23 14:32:35 -04:00
b2d0f5c56e
fmcadc4- use the same source/name for clocks
2015-10-23 14:32:35 -04:00
9d2b8809df
Makefiles: Updated Makefiles
2015-10-23 10:44:27 +03:00
cb2bda48c0
fmcadc5- gt/ip updates
2015-10-19 09:31:32 -04:00
ed918ec119
imageon - keeping scripts happy
2015-10-16 15:04:02 -04:00
e14e9294c5
project-names -- variables causes scripts to fail- too much parsing
2015-10-16 14:13:56 -04:00
36dd6427fe
pzsdr: Add untracked Makefiles
2015-10-16 13:58:36 +03:00
bbdc693954
pzsdr/all: Update Makefile
2015-10-16 11:57:51 +03:00
08777ca566
fmcadc5- latest board changes
2015-10-15 10:46:07 -04:00
030485de28
fmcadc5- regulators need a switching ref clock?
2015-10-15 10:46:07 -04:00
f966f79e5f
fmcadc5- regulators need a switching ref clock?
2015-10-15 10:46:07 -04:00
199227b78c
fix fmcjesdadc1_bd ILA warning
2015-10-13 10:19:08 -04:00
21737ad7b8
fmcomms2/zc706pr: Update the fifo interface of the PR module
2015-10-13 11:37:44 +03:00
c9a5057b93
library/prcfg : Split data bus to channels
...
Because of the new pack/upack modules on the data path, it makes more sense to split the data interface of the PR modules into separate channels.
The top module will supports max 4 channels.
2015-10-13 11:36:45 +03:00
9bb70e2b69
motcon2_fmc: Updated ZED project
2015-10-09 15:33:31 +03:00
83fb5c742a
motcon2_fmc: Updated project to Vivado 2015.2.1
...
- added cpack cores
- removed controller DMA paths
2015-10-09 13:56:41 +03:00
88e8bef92f
usdrx1: Update ZC706 project
2015-10-09 13:33:45 +03:00
02c0a5f5df
usdrx1: Update project to Vivado 2015.2.1
2015-10-09 13:33:07 +03:00
c83239b014
fmcomms2/zc706pr: Update PR design
...
+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:23:42 +03:00
09be227db9
fmcomms2/zc706pr: Update PR design
...
+ Add system_top.v to design
+ Add pr specific constraints
2015-10-09 13:19:09 +03:00
e4517c0d6a
daq2/common: Connect reset to dac fifo
2015-10-08 16:51:08 +03:00
df88b33946
usb_fx3: Initial commit
...
Only the UART connections are available.
The FMC should not be populated at this time
2015-10-02 09:30:31 +03:00
b93af3c21e
daq3- bd updates
2015-09-30 10:11:49 -04:00
81a1c21553
util_pmod_adc: Reset line changed to active low reset.
2015-09-30 12:33:46 +03:00
5f12c8c7d4
cftl_cip/common: Fix parameter names for dmac
2015-09-30 12:32:48 +03:00
3dc881dbb3
pmods/xfest14: Delete directory
...
This project will not be supported from the next release
2015-09-30 12:25:31 +03:00
e6af671bea
cn0363/zed: Fix DMAC parameter names
2015-09-30 11:31:53 +03:00
4aa4ffc25f
imageon/common: Update cores to Vivado 2015.2
2015-09-29 18:51:46 +03:00
e60d2f86b3
imageon/common: Fix parameter name for spdif_rx
2015-09-29 18:50:41 +03:00
b4252a8512
imageon_loopback: Delete directory
...
This project will not be supported from the next releases.
2015-09-29 14:53:44 +03:00
9832cea071
ad9739a_fmc: Common, reduced DMA fifo size
2015-09-28 12:19:23 +03:00
5b48340b08
fmcomms6: Updated ZC706 project
2015-09-28 11:32:20 +03:00
3b3c645827
fmcomms6: Updated project to Vivado 2015.2.1. Added cpack
2015-09-28 11:31:08 +03:00
046c89dacd
fmcomms2/pr: Delete the fmcomms2_pr directory
...
The fmcomms2/pr project is moved to fmcomms2/zc706pr
2015-09-25 19:11:43 +03:00
f77f928444
fmcomms2/zed: Fix the system_top
...
Fix the enable/txnrx control line.
2015-09-25 19:11:41 +03:00
aeb1d7aa3e
fmcomms2/zed: Cosmetic changes
2015-09-25 19:11:39 +03:00
f8b3096bd0
fmcomms2/vc707: Fix the system_top
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:37 +03:00
2c75cfd04e
fmcomms2/vc707: Cosmetic changes
2015-09-25 19:11:35 +03:00
ffa0bcd19f
fmcomms2/mitx045: Fix the system_top
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:32 +03:00
28d20e84c5
fmcomms2/zc702: Fix the system_top
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:30 +03:00
ea74413125
fmcomms2/kc705: Fix the system_top.
...
Fix the enable/txnrx control lines.
2015-09-25 19:11:28 +03:00
f80622b972
fmcomms2/ac701: Fix the system_top
...
Fix the enable/txnrx control line.
2015-09-25 19:11:26 +03:00
07e2d281c0
Make: Update Make files
2015-09-25 19:11:21 +03:00
1604e88242
fmcadc4: Update project to the new JESD interface framework
2015-09-25 19:11:19 +03:00
f4b432da08
fmcadc4: Update to 2015.2
2015-09-25 19:11:17 +03:00
4f99bdd93f
fmcadc5: Update project
...
+ Update the JESD IP core for Vivado 2015.2
+ Update the framework for JESD interface
2015-09-25 19:11:14 +03:00
f5b5bbfbca
fmcomms7: Update to the new JESD framework
...
Update project to the new framework for JESD interface and add a DAC FIFO to the transmit path.
2015-09-25 19:11:12 +03:00
fbd51c2734
fmcomms7: Update to 2015.2
...
Update IP core version of jesd204.
2015-09-25 19:11:10 +03:00
d198caa621
fmcomms2: Updated ZC702 design
2015-09-25 18:15:40 +03:00
4b115fbe69
ad9467_fmc: Delete ILA from the design
2015-09-25 17:41:46 +03:00
7853843036
fmcomms5: Update ZC706 project
2015-09-25 17:32:29 +03:00
108ffebae4
fmcomms5: Updated project to 2015.2.1
...
- added cpack / upack
2015-09-25 17:31:08 +03:00
848b51699c
fmcadc2: Updated VC707 project
2015-09-25 17:28:15 +03:00
e764f54426
fmcadc2: Updated ZC706 project
2015-09-25 17:26:54 +03:00
6fbd8dd9a5
fmcadc2: Update projecct to 2015.2.1
...
- updated to the new jesd framework
2015-09-25 17:25:32 +03:00
ab4b73fd32
ad6676evb: Updated VC707 project
2015-09-25 16:07:22 +03:00
33390c85f8
ad6676evb: Update ZC706 project
2015-09-25 14:46:02 +03:00
a49230ec07
ad6676evb: Updated project to 2015.2.1
...
- updated to the new jesd framework
- added cpack core
2015-09-25 14:44:46 +03:00
7f9c526683
fmcjesdadc1: VC707 update project
2015-09-24 19:50:14 +03:00
78fe05120b
fmcjesdadc1: Updated KC705 project
2015-09-24 19:14:48 +03:00
70c7c2aeb8
fmcjesdadc1: Updated ZC706 project
2015-09-24 19:14:05 +03:00
2ed161628d
fmcjesdadc1: Updated project to 2015.2.1
...
- updated to the new jesd framework
- added cpack core
2015-09-24 19:12:40 +03:00
58ab70bc0e
fmcomms1: Update AC701 project
...
Renamed mdio pin, as it's exported by the system wrapper
Renamed DMA parameter
2015-09-24 19:07:19 +03:00
f9801e8c85
pzsdr/cc*- rf card on fmc only
2015-09-23 09:16:41 -04:00
9832ea95a8
pzsdr/ccpci- initial version
2015-09-22 16:30:27 -04:00
14bccb6062
pzsdr/ccfmc- rf card/tdd only on fmc
2015-09-22 15:54:53 -04:00
fa5d879fdb
pzsdr/ccpci -- updates
2015-09-21 14:54:31 -04:00
fce96099ab
unused eth1 clocks
2015-09-21 14:54:31 -04:00
0702f2c231
ccpci- added
2015-09-21 09:31:18 -04:00
3a72d26f5b
pzsdr- pci carrier
2015-09-18 21:18:16 -04:00
9f8433159f
pzsdr- name changes
2015-09-18 16:24:27 -04:00
0d232a270a
pzsdr- breakout + fmc updates
2015-09-18 15:34:56 -04:00
3bd2bc4071
pzsdr- breakout + fmc updates
2015-09-18 15:34:36 -04:00
25f3f05c22
pzsdr- breakout + fmc updates
2015-09-18 15:33:50 -04:00
93b928033b
ccbrk- added
2015-09-18 13:24:26 -04:00
caec400378
pzsdr- make module default
2015-09-18 13:22:01 -04:00
236854c26f
pzsdr-cc-fmc updates
2015-09-18 12:46:42 -04:00
f970bf1786
pzsdr fmc carrier
2015-09-18 11:50:08 -04:00
b3a4f11e97
rfsom to pzsdr
2015-09-18 11:48:30 -04:00
0386bedff9
fmc carrier is -- ccfmc
2015-09-18 11:45:56 -04:00
92533bc24d
fmc carrier is -- ccfmc
2015-09-18 11:45:15 -04:00
48af5f29de
rfsom renamed to pzsdr
2015-09-18 11:19:50 -04:00
3ef94d559c
rfsom renamed to pzsdr
2015-09-18 11:18:59 -04:00
52d3f189a0
rfsom renamed to pzsdr
2015-09-18 11:18:01 -04:00
e2886eaa44
pzpcie- updates
2015-09-18 11:10:48 -04:00
379f788c8c
pzpcie- added
2015-09-18 11:10:48 -04:00
9e68357af5
usdrx1: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:19 +02:00
275830d2b1
motcon2_fmc: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:17 +02:00
8d179235f8
imageon: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:14 +02:00
9210e1d58a
fmcomms7: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:11 +02:00
39b032b868
fmcomms5: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:09 +02:00
cd8b467b1e
fmcomms2: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:07 +02:00
7e2255f4d9
fmcjesdadc1: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:05 +02:00
dd79dfdc12
fmcadc5: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:03 +02:00
7f5a22a75f
fmcadc4: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:28:01 +02:00
60490c4e2b
fmcadc2: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:59 +02:00
6c7316fbd0
daq3: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:56 +02:00
7184827d68
daq2: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:54 +02:00
f1fb599eb1
cn0363: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:51 +02:00
6d87f537da
cftl_cip: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:49 +02:00
1c603b830e
ad9467_fmc: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:47 +02:00
960c711f3b
ad9434_fmc: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:44 +02:00
7be1f62b8b
ad9265_fmc: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:25 +02:00
0f553a08e8
ad6676evb: Drop explicit axi_dmac clock synchronicity configuration
...
The axi_dmac core is now capable of detecting whether its different parts
run in different clock domains or not. No need to configure it manually any
more.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:21 +02:00
0021c7869d
kc705: Deactivated narrow burst support, as it's not needed
2015-09-16 19:02:17 +03:00
70cea5b14e
fmcomms1: Removed ILA
2015-09-16 18:51:40 +03:00
63aaa58861
ad9265_fmc: Updated project, removed ILA related clocks
2015-09-11 11:27:58 +03:00
a679251d7d
Makefiles: Update Make
2015-09-09 17:13:19 +03:00
f3eca48533
pzsdr_rfsom: Update project with the new TDD sync interface
2015-09-09 12:37:52 +03:00
510f1cfdd9
fmcomms2_zc706: Update project with the new TDD sync interface
2015-09-09 12:35:22 +03:00
f428d8bde9
adv7511: KC705, updated design so that the axi_hdmi_dma core has memory connection datawidth of 512
2015-09-08 16:43:40 +03:00
d81d8238a9
kc705: Updated mig project file
2015-09-08 16:42:23 +03:00
2757cd8baf
adv7511: AC701 fixed system top
2015-09-07 16:48:10 +03:00
214f5b18c1
no-trace option
2015-09-03 16:16:31 -04:00
00a55ded00
ibert to jesd-gt change
2015-09-03 16:16:30 -04:00
77ee3c4cbc
ibert to jesd-gt change
2015-09-03 16:16:28 -04:00
dbf7c154b2
no-trace option
2015-09-03 16:16:27 -04:00
e2aca435e5
ibert-to-jesd-gt change
2015-09-03 16:16:25 -04:00
f1d416a98b
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
1fff1076b1
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
01c0fdc809
daq2/a10gx- ethernet fix
2015-09-02 14:31:15 -04:00
1ecd615f92
common/mitx045 : Fix the vdma interface of axi_hdmi_core
2015-09-02 16:33:30 +03:00
9fb336e464
usdrx1: Add DDR FIFO
...
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.
Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.
Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
bbada6ed8f
usdrx1: Add overflow flag to ILA
...
It's useful to know if and when a overflow happens.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
c67aecc1eb
usdrx1: Disable SYNC_TRANSFER_START for the DMA
...
There is no sync signal in this design, so the flag needs to be set to 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
c00a6af4db
usdrx1: Add DDR FIFO
...
The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.
Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.
Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:21:45 +02:00
b73430d7ee
usdrx1: Add overflow flag to ILA
...
It's useful to know if and when a overflow happens.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:21:45 +02:00
b7de542e26
usdrx1: Disable SYNC_TRANSFER_START for the DMA
...
There is no sync signal in this design, so the flag needs to be set to 0.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:21:45 +02:00
9b37d6bfe7
pzslb- updates - wip
2015-08-31 15:41:29 -04:00
49430dc2b0
pzslb- copy
2015-08-31 15:41:27 -04:00
879a75a690
pzslb- copy
2015-08-31 15:41:26 -04:00
fdc3dbb805
pzslb- copy
2015-08-31 15:41:25 -04:00
fc79af6edc
pzslb- common
2015-08-31 15:41:24 -04:00
f005de9ee2
pzslb- added
2015-08-31 15:41:23 -04:00
a67ae238f8
rfsom-ps7- ddr settings
2015-08-31 15:39:45 -04:00
212235189f
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
0e20277bc1
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
93fe70790d
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
810fced1ec
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
01852a14de
hdmi-tx- signal name changes
2015-08-28 13:48:33 -04:00
7a1df720e2
rfsom- tdd ensm io changes
2015-08-27 16:26:18 -04:00
6e90ba24e4
rfsom- add rgmii iodelay constraints
2015-08-27 16:26:17 -04:00
15be942b74
daq2-a10gx- ignore cpu2ddr-io paths
2015-08-27 13:54:05 -04:00
a92e049e8f
fmcomms2_bd- another attempt at ila width
2015-08-27 13:17:08 -04:00
90e4cadf4b
daq2/kcu105- xcvr pin loc
2015-08-27 12:40:44 -04:00
b8f9b7040d
fmcomms2- tdd ila fixes
2015-08-27 11:55:41 -04:00
026fad8853
fmcomm2- enable/txnrx- through devif
2015-08-27 11:41:58 -04:00
6a9790484f
fmcomm2- enable/txnrx- through devif
2015-08-27 11:41:56 -04:00
3953ab5e22
rfsom- rgmii upgrade
2015-08-27 11:41:55 -04:00
7c8e56cb09
daq2/kcu105- pin loc is now all errors
2015-08-27 11:18:00 -04:00
89c7a4de79
daq2/kcu105- parameter changes
2015-08-27 11:18:00 -04:00
58fa29b673
daq2- jesd core upgrade
2015-08-27 11:18:00 -04:00
2e1e0939ce
fmcomms2- dma parameters & ila cores upgrade
2015-08-26 14:12:57 -04:00
74a6e33f2d
kcu105: 2015.2.1 updates
2015-08-25 09:12:36 -04:00
4eb28592c8
kcu105: 2015.2.1 updates
2015-08-25 09:12:32 -04:00
971e3395e7
projects/scripts: Update board part names.
...
Property 'board' is deprecated for object type 'project', 'board_part' is used. Update the 'board_part' property names for all Xilinx development boards.
2015-08-25 10:19:57 +03:00
77e2eb7364
projects/common: Fix parameter name for xilinx core axi_gpio
...
Parameter C_GPDATA_WIDTH is changed to C_GPIO_WIDTH.
2015-08-25 10:07:11 +03:00
d3e090da3d
projects/common: Upgrade Xilinx's IP cores
...
To update the projects to Vivado 2015.2 the following IP cores were upgraded:
+ microblaze 9.4 to microblaze 9.5
+ axi_ethernet 6.2 to 7.0
+ mig 6.1 to 7.0
2015-08-25 10:03:49 +03:00
203d7cb470
projects/common: Cosmetic changes.
2015-08-25 09:58:32 +03:00
f08305c979
adv7511_ac701: Fix axi_ethernet core's port connections
2015-08-25 09:54:19 +03:00
af8a48d90e
projects: Fix broken parameters at the common block designs.
...
Fix parameter names for axi_spdif_tx and axi_i2s_adi core instantiations.
2015-08-25 09:25:24 +03:00
78cf0fce0e
ddr/eth- pll refclock is defined by the cores
2015-08-21 14:42:15 -04:00
827fc1e29a
remove auto-pack disable
2015-08-20 13:54:16 -04:00
9e5e7d6805
remove rfsom from fmcomms2
2015-08-20 10:33:43 -04:00
168bcecc31
pzsdr- added
2015-08-20 10:32:48 -04:00
2dabf98089
parameter changes
2015-08-20 08:54:13 -04:00
0dfb3e2019
tcl_scripts: Update Vivado version number to 2015.2.1
2015-08-20 10:50:52 +03:00
d52308f074
axi_dmac: Change parameter name 2D_TRANSFER
...
Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER
2015-08-20 10:14:22 +03:00
0ec17fd4d6
daq2-a10gx- parameter changes
2015-08-19 14:56:00 -04:00
0e587dd955
daq2/a10gx-- ad-rst unpack
2015-08-19 13:26:38 -04:00
fdeeef3d77
daq2/a10gx-- intmem to ddr
2015-08-19 13:26:38 -04:00
e760aa424a
daq2/a10gx-- intmem to ddr
2015-08-19 13:26:38 -04:00
413c322145
base/daq2- updates
2015-08-19 13:26:38 -04:00
f40abf171f
cpack- adc_rst added
2015-08-19 13:26:38 -04:00
8cc3aa0865
ddr- 933/233
2015-08-19 13:26:38 -04:00
57cfb7cfb1
hdl/library: Update the IP parameters
...
The following IP parameters were renamed:
PCORE_ID --> ID
PCORE_DEVTYPE --> DEVICE_TYPE
PCORE_IODELAY_GROUP --> IO_DELAY_GROUP
CH_DW --> CHANNEL_DATA_WIDTH
CH_CNT --> NUM_OF_CHANNELS
PCORE_BUFTYPE --> DEVICE_TYPE
PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE
CHID --> CHANNEL_ID
PCORE_DEVICE_TYPE --> DEVICE_TYPE
PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N
PCORE_SERDES_DDR_N --> SERDES_DDR_N
PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE
DP_DISABLE --> DATAPATH_DISABLE
PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE
C_BIG_ENDIAN --> BIG_ENDIAN
C_M_DATA_WIDTH --> MASTER_DATA_WIDTH
C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH
NUM_CHANNELS --> NUM_OF_CHANNELS
CHANNELS --> NUM_OF_CHANNELS
PCORE_4L_2L_N -->QUAD_OR_DUAL_N
C_ADDRESS_WIDTH --> ADDRESS_WIDTH
C_DATA_WIDTH --> DATA_WIDTH
C_CLKS_ASYNC --> CLKS_ASYNC
PCORE_QUAD_DUAL_N --> QUAD_DUAL_N
NUM_CS --> NUM_OF_CS
PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID
PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID
PCORE_CLK0_DIV --> CLK0_DIV
PCORE_CLK1_DIV --> CLK1_DIV
PCORE_CLKIN_PERIOD --> CLKIN_PERIOD
PCORE_VCO_DIV --> VCO_DIV
PCORE_Cr_Cb_N --> CR_CB_N
PCORE_VCO_MUL --> VCO_MUL
PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC
PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH
PCORE_ADDR_WIDTH --> ADDRESS_WIDTH
DADATA_WIDTH --> DATA_WIDTH
NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS
DEBOUNCER_LEN --> DEBOUNCER_LENGTH
ADDR_WIDTH --> ADDRESS_WIDTH
C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED
Cr_Cb_N --> CR_CB_N
ADDATA_WIDTH --> ADC_DATA_WIDTH
BUFTYPE --> DEVICE_TYPE
NUM_BITS --> NUM_OF_BITS
WIDTH_A --> A_DATA_WIDTH
WIDTH_B --> B_DATA_WIDTH
CH_OCNT --> NUM_OF_CHANNELS_O
M_CNT --> NUM_OF_CHANNELS_M
P_CNT --> NUM_OF_CHANNELS_P
CH_ICNT --> NUM_OF_CHANNELS_I
CH_MCNT --> NUM_OF_CHANNELS_M
4L_2L_N --> QUAD_OR_DUAL_N
SPI_CLK_ASYNC --> ASYNC_SPI_CLK
MMCM_BUFIO_N --> MMCM_OR_BUFIO_N
SERDES_DDR_N --> SERDES_OR_DDR_N
CLK_ASYNC --> ASYNC_CLK
CLKS_ASYNC --> ASYNC_CLK
SERDES --> SERDES_OR_DDR_N
GTH_GTX_N --> GTH_OR_GTX_N
IF_TYPE --> DDR_OR_SDR_N
PARALLEL_WIDTH --> DATA_WIDTH
ADD_SUB --> ADD_OR_SUB_N
A_WIDTH --> A_DATA_WIDTH
CONST_VALUE --> B_DATA_VALUE
IO_BASEADDR --> BASE_ADDRESS
IO_WIDTH --> DATA_WIDTH
QUAD_DUAL_N --> QUAD_OR_DUAL_N
AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT
ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH
ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH
MODE_OF_ENABLE --> CONTROL_TYPE
CONTROL_TYPE --> LEVEL_OR_PULSE_N
IQSEL --> Q_OR_I_N
MMCM --> MMCM_OR_BUFR_N
2015-08-19 14:11:47 +03:00
10d9de39a1
axi_ad9361/tdd: Update the synchronization logic
...
The master will regenerate a sync pulse periodically. The period can be defined by software.
2015-08-19 12:21:23 +03:00
bcee3e04d4
fmcomms2_tdd: Update tdd_enabaled path
...
This line controls the mux, which switch between hdl and software (GPIO) control of the ENABLE/TXNRX pins.
Fix the broken path and change the name from "tdd_enable" to "tdd_enabled".
2015-08-19 12:14:05 +03:00
f5de5ca487
usdrx1: Fixed jesd core parameters. Fixed synchronization mechanism
2015-08-19 10:12:24 +03:00
e221c3b48c
daq2- gt changes
2015-08-17 14:11:58 -04:00
c72cf99562
daq2- gt changes
2015-08-17 14:11:58 -04:00
b84afcdcd1
Merge branch 'master' into dev
...
Conflicts:
library/Makefile
library/axi_ad6676/axi_ad6676_ip.tcl
library/axi_ad9122/axi_ad9122_core.v
library/axi_ad9122/axi_ad9122_ip.tcl
library/axi_ad9144/axi_ad9144_ip.tcl
library/axi_ad9152/axi_ad9152_ip.tcl
library/axi_ad9234/axi_ad9234_ip.tcl
library/axi_ad9250/axi_ad9250_hw.tcl
library/axi_ad9250/axi_ad9250_ip.tcl
library/axi_ad9361/axi_ad9361.v
library/axi_ad9361/axi_ad9361_dev_if_alt.v
library/axi_ad9361/axi_ad9361_ip.tcl
library/axi_ad9361/axi_ad9361_rx_channel.v
library/axi_ad9361/axi_ad9361_tdd.v
library/axi_ad9361/axi_ad9361_tx_channel.v
library/axi_ad9625/axi_ad9625_ip.tcl
library/axi_ad9643/axi_ad9643_channel.v
library/axi_ad9643/axi_ad9643_ip.tcl
library/axi_ad9652/axi_ad9652_channel.v
library/axi_ad9652/axi_ad9652_ip.tcl
library/axi_ad9671/axi_ad9671_constr.xdc
library/axi_ad9671/axi_ad9671_ip.tcl
library/axi_ad9680/axi_ad9680_ip.tcl
library/axi_ad9739a/axi_ad9739a_ip.tcl
library/axi_dmac/axi_dmac_constr.sdc
library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
library/axi_jesd_gt/axi_jesd_gt_constr.xdc
library/axi_jesd_gt/axi_jesd_gt_ip.tcl
library/axi_mc_speed/axi_mc_speed_constr.xdc
library/common/ad_gt_channel_1.v
library/common/ad_gt_common_1.v
library/common/ad_gt_es.v
library/common/ad_iqcor.v
library/common/ad_jesd_align.v
library/common/ad_rst.v
library/common/altera/ad_xcvr_rx_rst.v
library/common/up_adc_common.v
library/common/up_axis_dma_rx.v
library/common/up_axis_dma_tx.v
library/common/up_clkgen.v
library/common/up_clock_mon.v
library/common/up_dac_common.v
library/common/up_gt.v
library/common/up_hdmi_tx.v
library/common/up_tdd_cntrl.v
library/common/up_xfer_cntrl.v
library/common/up_xfer_status.v
library/util_cpack/util_cpack.v
library/util_cpack/util_cpack_ip.tcl
library/util_dac_unpack/util_dac_unpack_hw.tcl
library/util_jesd_align/util_jesd_align.v
library/util_jesd_xmit/util_jesd_xmit.v
library/util_upack/util_upack_ip.tcl
library/util_wfifo/util_wfifo.v
library/util_wfifo/util_wfifo_constr.xdc
library/util_wfifo/util_wfifo_ip.tcl
projects/arradio/c5soc/system_bd.qsys
projects/common/vc707/vc707_system_bd.tcl
projects/common/zc706/zc706_system_plddr3.tcl
projects/daq2/a10gx/Makefile
projects/daq2/a10gx/system_bd.qsys
projects/daq3/common/daq3_bd.tcl
projects/daq3/zc706/system_bd.tcl
projects/fmcjesdadc1/a5gt/Makefile
projects/fmcjesdadc1/a5gt/system_bd.qsys
projects/fmcjesdadc1/a5gt/system_constr.sdc
projects/fmcjesdadc1/a5gt/system_top.v
projects/fmcjesdadc1/a5soc/system_bd.qsys
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
projects/fmcomms1/ac701/system_bd.tcl
projects/fmcomms1/common/fmcomms1_bd.tcl
projects/fmcomms1/kc705/system_bd.tcl
projects/fmcomms1/vc707/system_bd.tcl
projects/fmcomms1/zc702/system_bd.tcl
projects/fmcomms1/zc702/system_top.v
projects/fmcomms1/zc706/system_bd.tcl
projects/fmcomms1/zc706/system_top.v
projects/fmcomms1/zed/system_bd.tcl
projects/fmcomms1/zed/system_top.v
projects/fmcomms2/ac701/system_constr.xdc
projects/fmcomms2/common/fmcomms2_bd.tcl
projects/fmcomms2/kc705/system_constr.xdc
projects/fmcomms2/kc705/system_top.v
projects/fmcomms2/mitx045/system_top.v
projects/fmcomms2/rfsom/system_constr.xdc
projects/fmcomms2/rfsom/system_top.v
projects/fmcomms2/vc707/system_top.v
projects/fmcomms2/zc706/system_bd.tcl
projects/fmcomms2/zc706/system_constr.xdc
projects/fmcomms2/zc706/system_top.v
projects/fmcomms2/zed/system_top.v
projects/imageon/zc706/system_constr.xdc
projects/motcon2_fmc/common/motcon2_fmc_bd.tcl
projects/motcon2_fmc/zed/system_constr.xdc
projects/motcon2_fmc/zed/system_top.v
projects/usdrx1/a5gt/Makefile
projects/usdrx1/a5gt/system_bd.qsys
projects/usdrx1/common/usdrx1_bd.tcl
Conflicts were resolved using 'Mine' (/dev).
2015-08-17 15:15:58 +03:00
17b2a9f121
Merge branch 'master'
...
Merge master into release to sync the index files. The two changes are just mode changes. There aren't any functional changes in this commit!
2015-08-17 10:09:07 +03:00
f08633c0d5
fmcomms2: Add GPIO to the c5soc project
2015-08-13 18:14:39 +03:00
c200fc8019
usdrx1: Updated a5gt project to Quartus 15
2015-08-12 10:20:58 +03:00
489b31e929
ad9434_fmc: DMAC's destination clock must be more than or equal to adc_clk/4 (125 Mhz)
...
DMAC's destination clock set to 200Mhz
2015-08-10 18:00:24 +03:00
10a3ce96fe
ad9434_fmc: DMAC's destination clock must be more than or equal to adc_clk/4 (125 Mhz)
...
DMAC's destination clock set to 200Mhz
2015-08-10 17:57:52 +03:00
afb9911b6e
Makefiles: Updated makefiles
2015-08-06 19:50:50 +03:00
d2c99acae8
fmcomms2/TDD: Update synchronization interface
...
Synchronization is done by a simple req/ack interface between a master and slave terminal.
2015-08-06 15:14:36 +03:00
cfc4046821
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-29 14:10:56 +03:00
8e631e56d6
fmcomms2: Add a synchronization interface for TDD mode.
...
Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write 0x01 into TDD register 0x50.
2015-07-28 14:42:54 +03:00
36f71ea59b
fmcjesdadc1: common altera, fixed dmac configuration and connection. Connected reset for cpack
2015-07-28 12:33:24 +03:00
0422c87846
a5soc/base- remove hdmi, led/switchs to gpio
2015-07-27 12:08:33 -04:00
2ca2bf9383
a5soc- all hps clocks
2015-07-27 12:08:33 -04:00
e488ba0287
a5soc- remove hdmi core
2015-07-27 12:08:32 -04:00
0c5958091e
fmcjesdadc1/a5soc- base/fmc split
2015-07-27 12:08:32 -04:00
0a5dc938cd
fmcjesdadc1/a5soc- base/fmc split
2015-07-27 12:08:32 -04:00
f5f9ec38e8
a5soc- base/fmc split
2015-07-27 12:08:32 -04:00
58e0884ff9
a5soc- board qsys file
2015-07-27 12:08:32 -04:00
4d7ff0ed15
a5gte: Update ethernet connections
2015-07-27 16:05:26 +03:00
31ab81d627
a5gt: Updated ethernet clock constraints
2015-07-27 16:02:51 +03:00
797d679c72
fmcomms2: Updated c5soc project with the latest cores. Tested with Quartus 15.0
2015-07-24 16:43:33 +03:00
816238bb6c
fmcjesdadc:A5gt, decreased destination bus width for DMAs to 256. Increased DMA FIFO to 32
...
With lower buswidth, if all 4 channels are captured some samples are lost
With fifo size of 64, there are timing violations in the DMAC
With this configuration, 65536 samples could be captured from all 4 channels with no sample lost
Because of the DMAC destination bus is 256, the number of samples to be captured must be a multiple of 16, otherwise the system will freeze. This will be corrected in software
2015-07-24 15:31:19 +03:00
289e73660b
removed- xcvr is now part of qsys
2015-07-23 15:26:51 -04:00
fb648ab6f5
moved to qsys
2015-07-23 15:26:21 -04:00
3ccf1bef36
base system modifications
2015-07-23 15:23:10 -04:00
a1733238df
fmcjesdadc1- base/board split up
2015-07-23 15:21:53 -04:00
3ea60bca5d
fmcjesdadc1: a5gt, design working with quartus 15.0
...
- added cpack to the design
- removed 166 MHz clock as it is not needed. DMA destination is 512 bits
- removed clock bridge between DMA and DDR
2015-07-23 18:11:53 +03:00
d8e2196c75
fmcjesdadc1- board qsys
2015-07-22 15:44:04 -04:00
d66387f482
fmcjesdadc1- board qsys
2015-07-22 15:23:39 -04:00
3e2712cf18
a5gt-base: initial updates
2015-07-22 15:22:22 -04:00
64070b6f27
a5gt- base system
2015-07-22 15:04:59 -04:00
b325c0fc01
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:22:07 +03:00
28aea82952
fmcomms2_zc702: Add SPI and GPIO interface for FREQCVT
2015-07-22 10:16:04 +03:00
b4eac232db
a10gx- move cores inside qsys
2015-07-21 11:06:45 -04:00
fcc298d837
a10gx- move cores inside qsys
2015-07-21 11:06:17 -04:00
b3102b5095
daq2/a10gx-- xcvr+base changes
2015-07-21 11:01:45 -04:00
445c4c835d
daq2-bd: xcvr components
2015-07-21 10:54:23 -04:00
08e46c5ff2
a10gx-base: data-master connections
2015-07-21 10:53:54 -04:00
97b8468819
daq2- constraints
2015-07-20 09:32:17 -04:00
1d6a77049d
daq2- base/board split
2015-07-20 09:31:57 -04:00
4b8d764852
daq2- base system modifications
2015-07-20 09:31:44 -04:00
da2e7acacb
daq2- separate base/board systems
2015-07-20 09:31:15 -04:00
2f53dc4412
daq2- board system only
2015-07-20 09:30:32 -04:00
a87b8fbf94
a10gx- base system only
2015-07-20 09:29:30 -04:00
80dc3bf92f
daq2/a10gx: remove signal tap
2015-07-16 14:59:01 -04:00
1de74c0267
fmcadc4: Changed the SPI CS address similar to previous version
2015-07-16 18:22:05 +03:00
c949482574
fmcadc4: Set explicit PCORE_ID for AD9680
2015-07-16 18:21:49 +03:00
a7da779b94
Makefile: Updated Makefiles
2015-07-16 18:19:42 +03:00
4e99a2cb01
xcvr: remove signal tap
2015-07-16 08:09:56 -04:00
7c142178dd
daq2/a10gx- axi_jesd_xcvr sysref name changes
2015-07-15 15:59:52 -04:00
ffd767deb2
daq2/a10gx- axi_jesd_xcvr sysref name changes
2015-07-15 15:59:51 -04:00
6c0ad6ede8
daq3: bsplit/ccat -- removed
2015-07-15 13:05:53 -04:00
a454b73d27
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:53 -04:00
2d8fa2024b
fmcjesdadc1/a5gt: split xcvr cores
2015-07-15 09:44:52 -04:00
226e23ca1f
fmcjesdadc1- xcvr components
2015-07-15 09:44:51 -04:00
3b3fe4e642
fmcomms2/FREQCVT : Update GPIOs
...
Add gpio_muxout_[tx/rx] GPIO lines and update SPI interface I/Os for the FREQCVT board
2015-07-15 15:34:45 +03:00
1dcbf5e5a2
fmcomms2/zc706: Fix GPIO connections
...
Fix GPIO connections for the FREQCVT board.
2015-07-15 15:12:01 +03:00
1f7745610e
daq2- ddr updates
2015-07-14 12:46:52 -04:00
a38339a3ec
fmcomms2/rfsom: Add GPIO control for the RF card
2015-07-14 13:12:54 +03:00
ba2029a6e8
fmcomms2/rfsom: Delete trailing whitespaces from system_constr.xdc
2015-07-14 13:12:53 +03:00
a37932d881
fmcadc4: Changed the SPI CS address similar to previous version
2015-07-14 11:11:33 +03:00
a2e7fb9491
daq2/a10gx: qsys signal tap version
2015-07-13 10:07:18 -04:00
825fddd034
transceiver split up outside qsys
2015-07-10 11:45:07 -04:00
8c0d74aa90
transceiver split up outside qsys
2015-07-10 11:44:42 -04:00
e40aac9ab6
transceiver split up outside qsys
2015-07-10 11:44:22 -04:00
30ea87e60b
fmcadc4: Set explicit PCORE_ID for AD9680
2015-07-09 19:55:58 +03:00
897c31ebbf
imageon: moved spdif_rx to DMA3 to be compatible with both zc706 and zed
2015-07-09 10:58:54 +03:00
f1dd2435b4
signal tap removed
2015-07-08 15:47:31 -04:00
c9e73b023d
signal tap removed
2015-07-08 15:46:52 -04:00
f64df40a0a
signal tap removed
2015-07-08 15:47:50 -04:00
19bf05c740
signal tap removed
2015-07-08 15:47:48 -04:00
c972779217
motcon2_fmc: updated util_gmii_to_rgmii and motcon2_fmc project for improved performance of the ethernet
...
- removed the delay controller from the top file and added it inside the util_gmii_to_rgmii core
- removed delay related xdc constraints as they are not needed
2015-07-08 16:23:33 +03:00
bbf1c5b803
transceiver core added/gpio removed
2015-07-07 15:30:38 -04:00
075b1e5424
daq2/a10gx: added axi_jesd_xcvr control
2015-07-07 10:22:36 -04:00
46fa91d5be
Makefile: Update Make files
2015-07-03 18:08:57 +03:00
8c98399c37
imageon_ZC706: Add axi_spdif_rx core to the design
2015-07-03 17:48:29 +03:00
27b786e92f
imageon_loopback: Use BUFIO for the HDMI clock buffer
...
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
02b5ce82ad
imageon_loopback: Invert transmit clock
...
The ADV7511 samples on the rising edge. Update the data on the falling
edge, this gives us a larger margin and improved signal stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
281cab091c
imageon_loopback: Create a clock for hdmi_rx_clock
...
Create a clock for the HDMI clock to make sure that the timing paths are
properly constraint.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:07:17 +02:00
5b2877b66f
imageon_loopback: Use BUFIO for the HDMI clock buffer
...
Since we are just doing a loopback all the logic is contained within the
IO bank. By using a BUFIO instead of a BUFG we avoid having to route the
clock signal from the IO bank to the middle of the FPGA and back to the IO
bank. This reduces the skew between clock and the data signals and makes
sure that the we can use the same design over a range of different
resolutions without having to calibrate the delay.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
f5fc3a4d2f
imageon_loopback: Invert transmit clock
...
The ADV7511 samples on the rising edge. Update the data on the falling
edge, this gives us a larger margin and improved signal stability.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
10cc007c57
imageon_loopback: Create a clock for hdmi_rx_clock
...
Create a clock for the HDMI clock to make sure that the timing paths are
properly constraint.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-03 15:06:03 +02:00
95500d4022
fmcomms2_rfsom: Fix GPIO connections
2015-07-03 13:03:19 +03:00
32ae7c771a
fmcomms2_ALL: Add/fix ENABLE/TXNRX control
...
Add ENABLE/TXNRX control for TDD, and preserve backward compatibility for pin control with GPIOs
2015-07-03 12:55:37 +03:00
5208ebedd5
Revert "fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control"
...
This reverts commit 6b15704b70
2015-07-03 10:20:50 +03:00
88f936cc86
imageon: Put HDMI input/output FF into the IOB
...
This gives us predictable delays as well as very small skew between the induvidual data lines.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:36:51 +02:00
94d1792aba
Revert "imageon: Connect raw data to ILA"
...
This reverts commit 9e4fb2d048
2015-07-02 18:36:51 +02:00
eb3a0c179b
imageon: Put HDMI input/output FF into the IOB
...
This gives us predictable delays as well as very small skew between the induvidual data lines.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-02 18:33:32 +02:00
e269fe1dd0
Revert "imageon: Connect raw data to ILA"
...
This reverts commit 9e4fb2d048
2015-07-02 18:33:32 +02:00
18e8914087
fmcjesdadc1/a5gt: pn-errors version
2015-07-01 13:43:12 -04:00
35aca98b5f
fmcjesdadc1/stap: added
2015-07-01 13:43:10 -04:00
68cb6df366
imageon: Connect raw data to ILA
...
Connect the raw HDMI data as generated by the ADV7604 to the ILA. For
debugging it is quite useful to be able to compare the data before and
after conversion pipeline.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
c8a095f79c
imageon: Increase ILA buffer size
...
2048 samples is not even enough for one 1080p line. Increase it to 4096.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
cb18b2c0fd
imageon: Fix HDMI RX DMA data ILA probe width
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The DMA data output of the HDMI RX core is 64-bit wide.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
c372064302
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-07-01 18:43:51 +02:00
6b15704b70
fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control
...
By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 15:26:46 +03:00
0102e3e02c
fmcomms2_ALL: Preserve backward compatibility for ENABLE/TXNRX control
...
By default the ENABLE/TXNRX pins are controlled by GPIOs, if the TDD module is enabled, the TDD FSM will take over the control of these two pins.
2015-07-01 13:54:01 +03:00
9e4fb2d048
imageon: Connect raw data to ILA
...
Connect the raw HDMI data as generated by the ADV7604 to the ILA. For
debugging it is quite useful to be able to compare the data before and
after conversion pipeline.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:03:03 +02:00
e429cb3f5c
imageon: Increase ILA buffer size
...
2048 samples is not even enough for one 1080p line. Increase it to 4096.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
bcd12c8ead
imageon: Fix HDMI RX DMA data ILA probe width
...
The DMA data output of the HDMI RX core is 64-bit wide.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-30 18:02:44 +02:00
330c205e8e
fmcjesdadc1- sys_clk changes
2015-06-30 10:47:21 -04:00
6bc24e25eb
stap- need to be qsys
2015-06-29 13:26:32 -04:00
d25e02d7ee
stap- need to be qsys
2015-06-29 13:26:20 -04:00
499357a65a
motcon2_fmc: Updated project to include XADC
...
- connected reset pin, as vivado reports the reset pin erroneously
- configured XADC in simultaneous sampling mode from XAUX0 and XAUX8
- connected XADC interrupt
- because in the project constraints some base pin constraints are overwritten, the project constraints are processed late
- GPI pins were assigned instead of the XADC GIO0 and GIO1, which were assigned to the XADC for external mux mode
- removed commented code
2015-06-29 16:56:25 +03:00
f32039f154
imageon: Hdmi_iic_rstn is accessible through a GPIO.
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Connect hdmi_iic_rstn to GPIO[33]
2015-06-29 10:49:59 +03:00
aef6f6b20b
imageon: Hdmi_iic_rstn is accessible through a GPIO.
...
Connect hdmi_iic_rstn to GPIO[33]
2015-06-29 10:48:57 +03:00
6862655b0d
Add .gitattributes file
...
Add .gitattributes file which sets up the eol encoding handling. This will
make sure that we get a uniform eol encoding across different operating
systems.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-26 11:07:10 +02:00
fcc185d769
Makefile: Updated makefiles
...
- removed up_drp_control, up_delay_control dependencies where not needed
- added axi_jesd_gt core in the library makefile
- fixed timing tcl dependency for altera projects
2015-06-25 14:59:34 +03:00
543e08b67a
fmcadc1: sdc updates
2015-06-25 04:25:39 -04:00
15740a7d34
fmcjesdadc1- 15.0 updates
2015-06-24 05:31:09 -04:00
714d415804
daq2/a10gx- signaltap changes
2015-06-19 14:33:04 -04:00
51e6a74a3d
daq2/a10gx- add xmit swap
2015-06-19 14:32:59 -04:00
d6b1260678
daq2/a10gx- signal tap + gpio
2015-06-19 14:32:58 -04:00
67df6b3ea8
a10gx- disable lab cell on dsp input register
2015-06-19 14:32:54 -04:00
db76fe3298
tquest- generate the timing report file
2015-06-19 14:32:53 -04:00
c3ea99d1f8
fmcadc2: Fixed zc706 spi connection
2015-06-19 13:31:59 +03:00
9fa705c488
fmcadc2: Fixed zc706 spi connection
2015-06-19 13:13:02 +03:00
301226c766
fmcjesdadc1: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:47 +03:00
f01ba54c5f
fmcomms1: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:33 +03:00
009d33f0a0
ad9467: Fixed mdc_mdio connection for kc705
2015-06-18 11:06:20 +03:00
41799c55dc
fmcjesdadc1: Fixed mdc_mdio connection for kc705
2015-06-18 11:04:29 +03:00
6de154d2c2
fmcomms1: Fixed mdc_mdio connection for kc705
2015-06-18 11:04:00 +03:00
988f4fac8f
ad9467: Fixed mdc_mdio connection for kc705
2015-06-18 11:03:11 +03:00
e6d9735e54
fmcomms1: Fixed zed top file, the DAC dma was not correctly connected
2015-06-17 14:43:34 +03:00
2e46bda916
motcon2_fmc: Update project to use the latest util_gmii_to_rgmii
2015-06-16 17:43:10 +03:00
8fc0e0e62d
fmcjesdadc1: Fixed vc707 ethernet connections
2015-06-16 16:27:09 +03:00
142f802f54
adv7511: Fixed vc707 ethernet connections
2015-06-16 16:26:58 +03:00
a2f380ab64
fmcjesdadc1: Fixed vc707 ethernet connections
2015-06-16 15:31:17 +03:00
98ae6d567f
adv7511: Fixed vc707 ethernet connections
2015-06-16 15:30:47 +03:00
4c80013faf
projects/daq2: gt lane split
2015-06-12 15:56:03 -04:00
e6525136a9
daq2/common: axi_ad9144_fifo needs a proper reset sequence
...
Connect the axi_ad9144_fifo/dma_rst signal to sys_cpu_reset
2015-06-12 14:03:46 +03:00
f587aa42d9
a10gx- tx sync
2015-06-10 14:32:25 -04:00
e3e4af5c51
daq2/zc706: open ports
2015-06-10 14:25:58 -04:00
97ab5e0ef7
fmcomms1: Update project to integrate the new util_wfifo
2015-06-10 15:16:17 +03:00
3d86f140e5
usdrx1: Removed ILA as the ports from axi_jesd_gt were removed
2015-06-10 10:56:55 +03:00
1fcdeac054
fmcjesdadc1/common: The new GT module does not have integrated monitor/debug ports
2015-06-09 11:50:55 +03:00
2330d1e27d
daq1/common: The new GT module does not have integrated monitor/debug ports
2015-06-09 11:50:27 +03:00
00b8c171b8
a10gx: pll locked to reset controller
2015-06-08 15:00:11 -04:00
be6d6f627a
ad9265: Removed ILA
2015-06-08 15:03:34 +03:00
25e56a4d03
arradio: renamed fmcomms2 c5soc to arradio
2015-06-08 11:35:21 +03:00
dc7064ab95
fmcomms2/vc707 - wfifo changes
2015-06-05 12:44:04 -04:00
25f1ad73f0
fmcomms2/freqcvt: Update SPI interface I/O
2015-06-05 18:16:14 +03:00
f1e75963a2
fmcomms2: wfifo+pack changes
2015-06-05 09:20:50 -04:00
47469ad375
ad9434/ad9467 : Connect reset signal for AXI streaming interface of the device dma
2015-06-04 18:09:48 +03:00
3b1ea7e528
axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch
...
598ece4c8d
2015-06-04 18:09:47 +03:00
a8a71b4971
alt-tq: common file
2015-06-04 11:00:25 -04:00
f81d22a17a
altera- common timing check
2015-06-04 10:56:32 -04:00
d111692608
daq2/a10gx- ddr-ref @133
2015-06-04 10:53:16 -04:00
886c24f597
tq-alt: added
2015-06-04 10:53:14 -04:00
264dbfed35
common: rfsom: Add constraints for the eth1 rx clock
...
Add clock rate constraints for the eth1 rx clock, otherwise the tools
assume the RX paths are unconstrained and creates a bitstream which
violates hold times which causes bit errors on the RX path.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-06-03 17:21:43 +02:00
71b5004b25
projects- drp moved to up-clock domain
2015-06-01 14:57:59 -04:00
f9ffaf457d
projects/daq2- drp moved to up clock
2015-06-01 13:39:26 -04:00
4a701d3895
a10gx- no-ddr
2015-06-01 11:00:02 -04:00
aa24c442f5
a10gx- no-ddr
2015-06-01 11:00:01 -04:00
5250635162
cn0363: Fix ad_iobuf signal names
...
The signal names for the ad_iobuf were recently changed, adjust the cn0363
project accordingly.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-27 13:25:19 +02:00
73d7bc111e
cn0363: Add missing Makefiles
...
Those were accidentally overlooked during the initial commit of the project.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-26 18:44:24 +02:00
77eff35d67
motcon2_fmc: Fixed constraint for renamed port
2015-05-23 19:02:48 +03:00
29ca9e4b8c
vc707: common, fixed address range for flash
2015-05-23 00:14:08 +03:00
8bd5fa5802
kc705: Common, fixed address range for the flash. Changed the start address so that it won't interfere with other cores
2015-05-23 00:10:06 +03:00
f91fbf1bc1
ad9434_zc706: Fix SPI interface
2015-05-22 12:31:48 +03:00
a6cae6b477
iobuf: do is a system verilog keyword
2015-05-21 14:06:17 -04:00
ad3198f623
a10gx: top level fixes
2015-05-21 14:06:15 -04:00
c9832d2f84
Remove ad7175_zed project
...
This project has been superseded by the cn0363 project and can be removed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
c53f8c15ee
Add CN0363 project
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Add support for the CN0363 (colorimeter) board connected to the ZED board.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 17:21:35 +02:00
6b9906b22b
Refresh Makefiles
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Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
ebbc0c6ed5
fmcomms5: zc706, removed debug related ila, as the pins were removed from the AD9361 IP
2015-05-21 14:19:22 +03:00
a047d3990a
fmcadc2_vc707: Fix interrupts
...
+ Remove some trailing whitespaces
+ Fix interrupt connections
2015-05-21 11:03:16 +03:00
19b094cab5
daq2/a10gx- added jesd align
2015-05-20 15:39:27 -04:00
f1c30ac225
daq2/a10gx- qsys updates
2015-05-20 14:24:49 -04:00
4927ca85c2
projects- jesd-align port name change
2015-05-20 14:24:26 -04:00
52b6077a46
a10gx- 15.0 updates
2015-05-19 15:12:23 -04:00
0805da3b6b
fmcomms2/rfsom- enable dac delay
2015-05-18 16:45:54 -04:00
3e51d29f75
enable/txnrx- tdd changes
2015-05-18 14:28:20 -04:00
c19749361d
Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
...
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
672a5a4dfa
a10gx- updates
2015-05-14 14:35:43 -04:00
b311b9dac6
a10gx- updates
2015-05-14 14:35:42 -04:00
3226ca4374
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
c28ff2ff9a
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
16541335e6
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
2cd1d8a591
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
0a6efaccca
fmcadc4- ad9680 version
2015-05-11 13:55:02 -04:00
848dac70d5
a10gx: updates--
2015-05-11 11:56:27 -04:00
dc0eea5f0f
a10gx: updates--
2015-05-11 11:56:26 -04:00
bdc3f3d807
a10gx: updates--
2015-05-11 11:56:24 -04:00
75e055dab9
daq2/a10gx- initial commit
2015-05-11 11:56:23 -04:00
515dfd88d4
a10gx- added
2015-05-11 11:56:22 -04:00
14b721682d
motcon1_fmc: Removed
2015-05-11 18:02:52 +03:00
3d4e9eb36a
ac701: common, commit ethernet reset pin
2015-05-11 16:41:28 +03:00
15618c9edf
daq2 : Integrate the DACFIFO into the supported projects.
...
+ All pack/unpack logic is made by the cpack and upack modules.
+ The DAC FIFO is integrated between the TX DMA and cpack.
+ All the top files are updated, all the projects compiled successfully.
2015-05-11 12:20:50 +03:00
bad821ba1c
sys_dmafifo: Update the p_sys_dacfifo process
...
Update the ports and parameters at util_dacfifo instantiation.
2015-05-11 12:20:47 +03:00
d9a124b767
fmcomms2_zc706: TDD integration, initial commit.
2015-05-11 12:20:45 +03:00
00335a2af2
Makefile: Fix ZC706 Makefiles with propper address for the mig file
2015-05-11 10:25:07 +03:00
81a20b4abb
rfsom- apisys lb updates
2015-05-08 15:22:17 -04:00
d515ab1b61
adv7511: AC701, update project to work at full HD resolution
2015-05-08 18:53:47 +03:00
293ec6a319
fmcomms2: c5soc project updated to 14.1
2015-05-08 17:44:16 +03:00
91279253ef
Makefiles: Added mig project file as a dependency for Microblaze based projects. Also updated usdrx1 a5gt Makefile
2015-05-08 15:31:40 +03:00
573acc8af6
usdrx1: A5GT project updated to 14.1
2015-05-08 15:04:44 +03:00
1c9b41db6f
fmcjesdadc1: A5GT project, added modular sgdma for Ethernet, nios configured for linux
2015-05-08 14:51:24 +03:00
68570c1815
vc707: Common system mig, updated datawidth to 256 from 128
2015-05-08 10:51:27 +03:00
d7a0f1ffe3
projects/imageon_loopback: Add the option of setting hdmi_iic_rstn externally.
2015-05-07 15:17:16 +03:00
949abcdc8f
Makefile: Updated makefiles so that the project recipe does not depend on lib
2015-05-06 14:58:29 +03:00
4f75414a1a
fmcomms1: Removed constraints that are not needed
2015-05-05 23:39:08 +03:00
1fcaf8fb63
fmcomms1: Updated AC701 project to meet timing. Reduced FIFO size for AD9643 DMA to 8
2015-05-05 23:37:01 +03:00
90a5bb81b6
cftl_cip: Updated project to work with the new util_pmod_adc core
2015-05-05 23:34:52 +03:00
95805f21fa
adv7511: Fixed system_top for mitx045 board
2015-05-05 10:08:11 +03:00
3517b6941c
adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale
2015-05-05 10:06:26 +03:00
319f821fab
zc706pr - makefile
2015-05-04 13:41:03 -04:00
ab85e2ba36
zc706pr - 706 partial reconfiguration
2015-05-04 12:36:57 -04:00
e489090fbb
scripts- initialize prcfg list
2015-05-04 12:34:19 -04:00
2a8703763e
zc706pr - 706 partial reconfiguration
2015-05-04 12:33:28 -04:00
c3dd9258e7
zc706: project mode
2015-05-04 10:25:12 -04:00
62acd37fee
zc706: project mode
2015-05-04 10:25:07 -04:00
e7a0da9089
fmcomms2 : Verify the existence of the PR license
...
The fmcomms2 runs by default on PR mode, if the project script does not find a PR license, will implement just the default mode.
2015-05-04 15:12:38 +03:00
4bb26caa13
itx045: default install
2015-05-01 16:19:10 -04:00
ad551a0073
itx045: updates
2015-05-01 16:18:43 -04:00
aced144916
itx045: updates
2015-05-01 16:18:23 -04:00
ff443655ca
itx045: add ps7 settings
2015-05-01 16:17:59 -04:00
26fb85583b
adi_project- prefix directory for gitignore & make clean
2015-05-01 13:18:12 -04:00
00cafd4df0
fmcomms2/zc706: add partial reconfiguration
2015-05-01 12:23:18 -04:00
3641d8f714
fmcomms2/zc706: add partial reconfiguration
2015-05-01 12:23:11 -04:00
75a81d67d8
fmcomms2/zc706: add partial reconfiguration
2015-05-01 12:23:07 -04:00
0dc4c9cda9
adi_project: added partial reconfiguration
2015-05-01 12:21:59 -04:00
140c622c8b
prcfg: common files
2015-05-01 11:48:09 -04:00
a8d4c916c1
fmcomms2_bd: remove axi3 switch
2015-05-01 11:47:29 -04:00
3b58785368
daq1: Updated jesd reset connection. Fixed dmac async configuration. Updated zc706 constraints
2015-04-30 12:14:03 +03:00
e332fa01c8
ad6676evb, daq2, fmcadc2, fmcjesdadc1, usdrx1: Updated jesd reset connection
2015-04-30 12:11:46 +03:00
1df48a2e6e
Add hdmiio_int pin.
2015-04-29 18:50:28 +03:00
19ef85cec3
vc707: Changed mig project to use BANK_ROW_COLUMN, as it seems this mode gives best performance
2015-04-28 17:15:58 +03:00
288b9cccff
Makefile: Added makefiles for imageon_loopback project. Updated axi_ad9152, util_gmii_to_rgmii, util_wfifo to include constraints file
2015-04-28 15:22:37 +03:00
252aa135eb
ad9739a: Changed dma and interconnect clock to 200mhz. Removed div_clk constraint, as it is autodetected
2015-04-28 15:14:31 +03:00
3fdda617a4
fmcomms1: updated common, changed DMAC fifo size and wfifo reset signal source
...
- changed DMAC FIFO size to 16, as it should be large enough
- connected wfifo reset to adc_rst from axi_ad9643 core
2015-04-28 14:58:04 +03:00
37bfb2ef4b
ad9265: Updated common, wfifo is reset by the adc_rst signal from axi_ad9265 core
2015-04-28 14:53:12 +03:00
1eebfd3155
projects/imageon_loopback: Initial commit.
2015-04-28 10:32:28 +03:00
e51edfbadb
adv7511: KC705 mdio pin name fix
2015-04-27 11:21:36 +03:00
7e6f2bfa15
ad9265: Updated constraints file.
2015-04-27 11:20:42 +03:00
272148eee5
rfsom: sdio 50mhz
2015-04-23 15:30:50 -04:00
7611c2ae17
kcu105: ddr mig rbc to rcb
2015-04-23 15:30:48 -04:00
bb185296d7
fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples.
...
The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells.
This is a the maximum BRAM FIFO depth in case of the VC707.
2015-04-23 18:00:00 +03:00
f232a36141
common: Place HDMI interface registers into the IOB
...
The paths from the HDMI interface registers to the IO pads are
unconstrained. This means the P&R can in theory put the register anywhere
which could lead to stability issues on the interface, depending on what
else is in the fabric. To get predictable delays for the register to IO pad
path place the register into the IOB section.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
bd6c76f4ab
fmcomms5: Set DMA AXI type to AXI3 on ZYNQ
...
The HP memory ports on ZYNQ are AXI3. The AXI-DMAC supports both native AXI3
and AXI4, by configuring it for AXI3 there is no need for a protocol
converter inside the interconnect, that connects the DMAC to the HP port.
In addition to that also set the data width for the DMAC on the HP port side
to 64 so there is no need for a memory width converter in the interconnect.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
4ed7c9aee9
fmcomms2_pr: zc706: Fix ddr and fixed_io signal names
...
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
558f2e89af
imageon: zc706: Fix ddr and fixed_io signal names
...
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
1bb5b6e55f
adv7511: zc706: Fix ddr and fixed_io signal names
...
The toplevel input/output signal names are lower case, but the signals
connected to the system_wrapper are upper case. Since verilog is case
sensitive this leaves the toplevel input/output signals unconnected. Fix
this by using lower case names everywhere.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-23 14:33:47 +02:00
a61a195e3f
Makefiles: Updated makefiles to add the new constraints as dependecies
2015-04-23 11:16:39 +03:00
e25cfb9d9f
rfsom: ddr configuration
2015-04-22 13:45:11 -04:00
a100ecd308
util_dacfifo: Update BRAM DAC Fifo
...
The fifo will be placed between the DMAC and the Upack module, all the interfaces were updated.
2015-04-21 15:45:56 +03:00
3fd830b038
fmcomms2: Use AXI3 interface for the DMA on ZYNQ
...
On ZYNQ the HP interconnects have a AXI3 interface. The DMA controller
supports both AXI4 and AXI3. By switching to AXI3 there is no need to create
a protocol converter between the DMA and the HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:51:37 +02:00
71d4f3a474
fmcomms2: Don't mark synchronous paths as asynchronous for the DMAs
...
The AXI master interface and the register map AXI slave interface use the
same clock. No need to mark the interfaces as asynchronous. This removes the
need for CDC logic on those paths.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:51:37 +02:00
dc2b37bd0c
Makefile: Added top level Makefile. Modified behavior of clean and clean-all
...
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.
The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
374f82e7de
makefiles: The clean command for library won't remove the xml files, except for component.xml.
...
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
8b5d1a8693
fmcadc2: Connect the second CS line for the external SPI interface
2015-04-15 19:08:17 +03:00
780455d68c
Makefile: Updated makefiles. Added makefiles for altera
2015-04-09 17:57:06 +03:00
afea42f444
rfsom: Use interface connection for the I2S stream
...
Use a interface connection for the I2S stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:26 +02:00
90e132d203
mitx045: Use interface connection for the I2S stream
...
Use a interface connection for the I2S stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
7f26bfe436
zed: Use interface connection for the I2S stream
...
Use a interface connection for the I2S stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
06e37b0082
common: zed: Use interface to connect I2C core to the I2C mixer
...
Use a interface connection for the I2C connection instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
7da59a435f
common: rfsom: Use interface connection for the HDMI DMA stream
...
Use a interface connection for the HDMI DMA stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
1f2ecaf037
common: mitx045: Use interface connection for the HDMI DMA stream
...
Use a interface connection for the HDMI DMA stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
1d66cf63b6
common: zc706: Use interface connection for the HDMI DMA stream
...
Use a interface connection for the HDMI DMA stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
ab5c7bb57b
common: zc702: Use interface connection for the HDMI DMA stream
...
Use a interface connection for the HDMI DMA stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
70deb1eed1
common: zed: Use interface connection for the HDMI DMA stream
...
Use a interface connection for the HDMI DMA stream instead of individually
connecting each of the signals. This make things a bit cleaner.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
38722e569b
common: zed: Fix audio DMA reset signals
...
Make sure to connect the I2S and SPDIF core DMA reset signals to the correct net.
Fixes audio support on the ZED board.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
5f8e9a74ea
makefile: updated
2015-04-07 16:32:01 -04:00
6d0a2bf64c
axi_adcfifo: added
2015-04-07 16:21:39 -04:00
4f7f109056
util_adcfifo: added
2015-04-07 16:08:38 -04:00
02dfa865b4
fmcadc5_vc707: Fix system top.
2015-04-06 12:15:49 +03:00
0a8823361f
fmcjesdadc1/a5gt: 14.1 updates
2015-04-03 14:54:57 -04:00
3aac5f9494
fmcjesdadc1/a5gt: 14.1 updates
2015-04-03 14:54:55 -04:00
5abf60345c
fmcomms7: dac lane mux
2015-04-03 13:42:27 -04:00
26a1f48724
fmcomms7: dac lane mux
2015-04-03 13:42:27 -04:00
0b00073ce5
rfsom: add ddr parameters
2015-04-03 13:42:27 -04:00
49b8d389f6
fmcjesdadc1: Kc705, fixed system top,SPI
2015-04-03 18:28:26 +03:00
5afcfa37a7
ad6676evb: changed the dma clock
2015-04-03 18:27:46 +03:00
f79a152958
Makefiles: updated all makefiles adding clean functionality
2015-04-03 11:57:54 +03:00
51b5e4ddc5
fmcomms5: Moved the clock generation for dma transfer inside system_bd of the platform
2015-04-02 22:29:17 +03:00
a8b2292370
ad9265: Changed the dma clock
2015-04-02 22:27:55 +03:00
f15ff45afc
imageon_zed: Initial commit plus fix ILAs
2015-04-02 18:53:45 +03:00
2937445cce
fmcomms2_pr: Update project to the new frame work.
2015-04-02 16:06:08 +03:00
9745462d88
fmcomms2: VC707 fixed top file
2015-04-02 15:31:40 +03:00
9dac22c814
fmcomms2: ZC702 fixed GPIOs in top file
2015-04-02 15:30:41 +03:00
243a9bc992
fmcomms1: AC701 update project to new framework
2015-04-02 15:30:02 +03:00
0162009099
cftl_cip: Update project to the new frame work.
2015-04-02 15:14:04 +03:00
8ed301a264
AC701: Common, removed system clock constraint
2015-04-02 11:51:20 +03:00
408dc6f018
ac701_base: Change data and instruction memory range to 8kbyte
2015-04-02 11:34:20 +03:00
dbbdeeaa0c
fmcomms1: Updated AC701 project to new framework
2015-04-02 11:22:16 +03:00
a4e9dd5fc4
fmcomms2: KC705 updated project
2015-04-02 11:21:13 +03:00
0184d2a4c7
makefile: added
2015-04-01 16:30:05 -04:00
a16ded55cf
makefile: added
2015-04-01 16:30:04 -04:00
ef32088c25
makefile: added
2015-04-01 16:30:03 -04:00
d7671ecf6d
makefile: added
2015-04-01 16:30:02 -04:00
a7d40aa0f2
makefile: added
2015-04-01 16:30:00 -04:00
e9a4a41823
makefile: added
2015-04-01 16:29:59 -04:00
9dba2d1e3b
makefile: added
2015-04-01 16:29:58 -04:00
c0b0abd8b7
makefile: added
2015-04-01 16:29:57 -04:00
36868c5433
makefile: added
2015-04-01 16:29:55 -04:00
fe8fb8f5ed
makefile: added
2015-04-01 16:29:54 -04:00
c63dead379
makefile: added
2015-04-01 16:29:53 -04:00
5165129c92
makefile: added
2015-04-01 16:29:52 -04:00
1697f297f8
makefile: added
2015-04-01 16:29:50 -04:00
59698474af
makefile: added
2015-04-01 16:29:49 -04:00
596d9db915
makefile: added
2015-04-01 16:29:48 -04:00
968836011f
makefile: added
2015-04-01 16:29:47 -04:00
c99630cb49
makefile: added
2015-04-01 16:29:45 -04:00
a9fe02419e
makefile: added
2015-04-01 16:29:44 -04:00
15ad9c287f
makefile: added
2015-04-01 16:29:43 -04:00
c46866e78c
makefile: added
2015-04-01 16:29:42 -04:00
c5a67ad1cd
makefile: added
2015-04-01 16:29:41 -04:00
74d3d458da
makefile: added
2015-04-01 16:29:39 -04:00
b1cc047d04
makefile: added
2015-04-01 16:29:38 -04:00
25a6a75a32
makefile: added
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c5ccd44ffb
makefile: added
2015-04-01 16:29:36 -04:00
006a4fd209
makefile: added
2015-04-01 16:29:34 -04:00
61bdb437b1
makefile: added
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970d5f8c3e
makefile: added
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5f149535b5
makefile: added
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48e8945ac1
makefile: added
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1c1464876c
makefile: added
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56615a19f2
makefile: added
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1a14a36db6
makefile: added
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c085fbdd35
makefile: added
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077d2699fe
makefile: added
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d50bf705ef
makefile: added
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9e8cb22c96
makefile: added
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0a62cc9b8e
makefile: added
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661cdc5752
makefile: added
2015-04-01 16:29:18 -04:00
0275f5575b
makefile: added
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b7d72a5b2e
makefile: added
2015-04-01 16:29:16 -04:00
71adb70844
makefile: added
2015-04-01 16:29:14 -04:00
1165203964
makefile: added
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e596a1c593
makefile: added
2015-04-01 16:29:12 -04:00
6391b9aa9d
makefile: added
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565839db38
makefile: added
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14c36b172f
makefile: added
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ae960e66e9
makefile: added
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f3c151eb7c
makefile: added
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12e9ab7bdd
makefile: added
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4e3e26a8dd
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b6d5e21133
makefile: added
2015-04-01 16:29:02 -04:00
0dc0d825a6
makefile: added
2015-04-01 16:29:01 -04:00
283427647b
makefile: added
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61293e7231
makefile: added
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73b31cfea0
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79a07e737d
makefile: added
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b3c666cf0d
makefile: added
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7a505f2d81
makefile: added
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8c25254fd7
makefile: added
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0664fb76f0
makefile: added
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3051afd7da
makefile: added
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d8ca123557
makefile: added
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88676c8c00
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2015-04-01 16:28:47 -04:00
786690cdae
makefile: added
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861341df2d
makefile: added
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69e817aed7
makefile: added
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8595341c32
makefile: added
2015-04-01 16:28:42 -04:00
1c558f23db
makefile: added
2015-04-01 16:28:41 -04:00
d5562e6a63
makefile: added
2015-04-01 16:28:39 -04:00
47331d951a
makefile: added
2015-04-01 16:28:38 -04:00
2c8939f246
makefile: added
2015-04-01 16:28:37 -04:00
9ca85e9837
makefile: added
2015-04-01 16:28:36 -04:00
4a197f532e
makefile: added
2015-04-01 16:28:34 -04:00
26f176f2b5
makefile: added
2015-04-01 16:28:33 -04:00
f330a82bb5
makefile: added
2015-04-01 16:28:32 -04:00
544d4f579f
makefile: added
2015-04-01 16:28:30 -04:00
2fdc3d6d96
makefile: added
2015-04-01 16:28:29 -04:00
df7c64be5f
makefile: added
2015-04-01 16:28:28 -04:00
3520884406
makefile: added
2015-04-01 16:28:27 -04:00
aa1739cb3e
makefile: added
2015-04-01 16:28:25 -04:00
affa42d76a
makefile: added
2015-04-01 16:28:24 -04:00
c87268e703
makefile: added
2015-04-01 16:28:23 -04:00
4cf4349e27
makefile: added
2015-04-01 16:28:22 -04:00
98c2deaf26
imageon_zc706: Update project
...
+ Connect the Rx path to HP2
+ Enable AXI_SLICE_DEST
+ Add ILA to the dma_fifo and dma_axi_s2mm interface
+ Fix constraints
2015-04-01 18:50:18 +03:00
271a383012
ad9467_kc705: Update project to the new frame work.
2015-04-01 17:16:47 +03:00
1819a41ab5
ad9467_zed: Update project to the new framework.
2015-04-01 14:38:39 +03:00
fbfbfdaf87
motcon2_fmc: Updated to the latest framework
2015-04-01 11:45:01 +03:00
e58e9bc701
fmcomms5: Updated zc702 project to the latest framework
2015-03-31 17:44:09 +03:00
fb3ee53790
fmcomm5: Updated ZC706 project
2015-03-31 17:43:30 +03:00
92aa58826d
fmcomms5: Updated project to be compatible with both ZC702 and ZC706
2015-03-31 17:42:44 +03:00
207b9679c9
fmcomms2: miniITX project updated to the new framework
2015-03-31 16:17:58 +03:00
bf1a50ef0c
mitx: common, fixed number of gpios enabled
2015-03-31 16:16:40 +03:00
7d1c715f09
adv7511_vc707: Fix system top.
2015-03-31 11:00:48 +03:00
8f2fdec838
ad6676evb/vc707: 2014.4 updates
2015-03-30 14:59:09 -04:00
c4a7730c89
ad6676evb/vc707: 2014.4 updates
2015-03-30 14:59:09 -04:00
7f2cc2117c
ad6676evb/vc707: 2014.4 updates
2015-03-30 14:59:09 -04:00
edcc0672d2
ad6676evb/vc707: 2014.4 updates
2015-03-30 14:59:09 -04:00
7aeeaec5f4
fmcomms1: VC707 updated to the latest framework
2015-03-30 18:09:57 +03:00
89b83f8a00
fmcomms1: KC705 project updated to the latest framework
2015-03-30 18:09:17 +03:00
11379939d0
fmcjesdadc1: VC707, Updated project to the latest framework
2015-03-30 18:08:19 +03:00
c7e4ba5083
fmcjesdadc1: Updated KC705 to the latest flow
2015-03-30 18:07:47 +03:00
4f69ae19c5
adv7511_mitx045: Update latest frame work.
2015-03-30 17:54:37 +03:00
fcb163062f
adv7511 : Fix top for kcu105 and kc705
2015-03-30 16:21:38 +03:00
c00633d1ac
adv7511_ac701: Update project and common files to the new framework.
2015-03-30 15:23:26 +03:00
166c78060c
adv7511_vc707: Fix system top.
2015-03-29 16:17:08 +03:00
7e539632e5
adv7511_kc705: Fix system top.
2015-03-29 16:16:11 +03:00
e116822059
imageon_zc706: Updates and fixes
...
+ sync the sof to the dma_de signal
+ hdmi_rx_dma is connected to the HP1
+ fix syncronization signal in the CSC module
+ hdmi_rx_clk is asynchronous
2015-03-27 18:57:32 +02:00
e7c33bc7d8
ad9265_fmc: Fixed spi connection. Changed ila clock to 200 MHz
2015-03-27 15:40:28 +02:00
01f8c373b0
fmcomms1: Updated zc702 project to the latest framework
2015-03-27 15:38:46 +02:00
dbcf8389b3
fmcomms1: Updated zed project to the latest framework
2015-03-27 15:37:50 +02:00
8bc589a4d4
fmcadc2/vc707: 2014.4 updates
2015-03-26 15:07:17 -04:00
a24c1d33e9
fmcadc2/vc707: 2014.4 updates
2015-03-26 15:07:15 -04:00
86512ad95a
fmcadc2/vc707: 2014.4 updates
2015-03-26 15:07:10 -04:00
cf85f0b0bb
daq2/vc707: gpio_bd is 21bits
2015-03-26 14:18:26 -04:00
90a8d91c36
daq2/vc707: 2014.4 updates
2015-03-26 14:02:43 -04:00
17918bf735
daq2/vc707: 2014.4 updates
2015-03-26 14:02:39 -04:00
6b1eac4211
daq2/vc707: 2014.4 updates
2015-03-26 14:02:34 -04:00
6a85724793
daq2/vc707: 2014.4 updates
2015-03-26 14:02:31 -04:00
5014b4209c
kc705/vc707: consistency fixes
2015-03-26 14:02:10 -04:00
67c8d02110
kc705/vc707: consistency fixes
2015-03-26 14:00:58 -04:00
1fcccacdf5
kc705/vc707: consistency fixes
2015-03-26 14:00:50 -04:00
276bb9525a
daq2/kc705: 2014.4 updates
2015-03-26 10:14:12 -04:00
a7e3d2af67
daq2/kc705: 2014.4 updates
2015-03-26 10:14:12 -04:00
803ef90fea
daq2/kc705: 2014.4 updates
2015-03-26 10:14:12 -04:00
daac204676
kc705: gpio bd
2015-03-26 10:14:12 -04:00
ee2cd034bc
scripts: add gnd/vcc connections
2015-03-26 10:08:01 -04:00
f1e542abe3
adv7511_vc707: Constraint file added.
2015-03-26 13:03:51 +02:00
2d05193093
adv7511_zc702: Update project to the new framework.
2015-03-26 12:20:31 +02:00
d1e4727066
adv7511_vc707: Update project to the new framework.
2015-03-26 12:20:30 +02:00
feb29d57a5
adv7511_kcu105: PCORE_DEVICE_TYPE is a carrier specific parameter.
...
Move the PCORE_DEVICE_TYPE parameter from common to system_bd.
2015-03-26 12:20:28 +02:00
7c289c8844
adv7511_kc705: Update project to the new framework.
2015-03-26 12:20:27 +02:00
ccf0542218
fmcjesdadc1: Connected constant 0 to unconnected inputs
2015-03-26 12:08:14 +02:00
1828a94446
fmcomms5: Updated common and ZC706 project to the latest framework
2015-03-25 17:42:11 +02:00
10f3ac4d22
fmcomms1: Updated common and ZC706 project to the latest flow
2015-03-25 17:41:14 +02:00
037484e1d0
usdrx1: Updated project to the latest framework
2015-03-25 17:39:51 +02:00
754f11e0e6
imageon: updates
2015-03-24 15:08:48 -04:00
007a1ea3a4
imageon: updates
2015-03-24 15:08:48 -04:00
0085b8a712
imageon: updates
2015-03-24 15:08:48 -04:00
4bb8712e71
imageon: updates
2015-03-24 15:08:48 -04:00
b774379796
fmcomms2_zc706: Clean up system top
2015-03-24 13:38:48 +02:00
fcbbfa0177
fmcomms2_pr ZC706: Update project to the new framework
2015-03-24 13:37:37 +02:00
75d2c7e93e
daq1_zc706: Update project to the new framework
2015-03-24 12:45:24 +02:00
d418c9f9b1
fmcjesdadc1: Updated project to new flow. Updated ZC706 design
2015-03-24 10:38:14 +02:00
58a5e0142c
ad9265_fmc: Updated project to the new flow
2015-03-24 10:37:06 +02:00
919c02b57a
cftl_std: Update project to the new framework
2015-03-23 16:03:15 +02:00
d93b967980
fmcadc5: 2014.4 updates
2015-03-23 10:00:46 -04:00
624d2778d8
fmcadc5: 2014.4 updates
2015-03-23 10:00:46 -04:00
6dca97dd20
fmcadc5: 2014.4 updates
2015-03-23 10:00:46 -04:00
a09075030c
fmcadc5: 2014.4 updates
2015-03-23 10:00:46 -04:00
a74c61d6d5
vc707: gpio_bd changes
2015-03-23 10:00:46 -04:00
7c921474bf
adv7511_zed: Update project to the new framework
2015-03-23 13:01:51 +02:00
8443e94442
ad9434_fmc: Update project to the new framework
2015-03-23 13:00:50 +02:00
43673f6b9d
imageon_zc706: Update the project to the new framework
2015-03-23 12:45:34 +02:00
c1c6787b91
fmcomms2: Updated VC707 design with the latest base design
2015-03-20 18:22:48 +02:00
69326a72ef
VC707: Updated base design
2015-03-20 18:20:44 +02:00
b12187433d
adv7511_zc706: Interrupts and framework updates
2015-03-20 13:30:24 +02:00
cba3dde3dc
fmcadc4: 2014.4 updates
2015-03-19 16:33:14 -04:00
9e1e4969ff
fmcadc4: 2014.4 updates
2015-03-19 16:33:14 -04:00
9f727776e9
fmcadc4: 2014.4 updates
2015-03-19 16:33:14 -04:00
34d95c1969
fmcadc4: 2014.4 updates
2015-03-19 16:33:14 -04:00
1354836799
fmcadc4: 2014.4 updates
2015-03-19 16:33:14 -04:00
7e0bfca0c6
fmcadc4: 2014.4 updates
2015-03-19 16:33:14 -04:00
ee87421419
fmcomms6: 2014.4 updates
2015-03-19 15:36:52 -04:00
4d91d85265
fmcomms6: 2014.4 updates
2015-03-19 15:36:51 -04:00
5192adf5a7
fmcomms6: 2014.4 updates
2015-03-19 15:36:50 -04:00
c8d60d249b
fmcomms6: 2014.4 updates
2015-03-19 15:36:48 -04:00
9571ce3e3b
fmcomms6: 2014.4 updates
2015-03-19 15:36:47 -04:00
de14146b0b
fmcadc2: 2014.4 updates
2015-03-19 13:22:30 -04:00
771215cbbc
fmcadc2: 2014.4 updates
2015-03-19 13:22:30 -04:00
01de3e7984
fmcadc2: 2014.4 updates
2015-03-19 13:22:30 -04:00
b4bee697cb
fmcadc2: 2014.4 updates
2015-03-19 13:22:30 -04:00
126158629c
fmcadc2: 2014.4 updates
2015-03-19 13:22:30 -04:00
275ce42bc9
daq3: 2014.4 updates
2015-03-19 12:45:55 -04:00
caa0e27bd6
daq3: 2014.4 updates
2015-03-19 12:45:54 -04:00
423b436601
daq3: 2014.4 updates
2015-03-19 12:45:52 -04:00
0c94ea8d2b
daq3: 2014.4 updates
2015-03-19 12:45:51 -04:00
2fa475cca2
daq3: 2014.4 updates
2015-03-19 12:45:50 -04:00
ec0b6ac754
ad9739a/zc706: 2014.4 updates
2015-03-19 11:36:27 -04:00
c236c38e93
ad9739a/zc706: 2014.4 updates
2015-03-19 11:36:27 -04:00
18112d723f
ad9739a/zc706: 2014.4 updates
2015-03-19 11:36:27 -04:00
8542c2b0d7
rfsom: sd1 to sd0 changes
2015-03-19 09:34:15 -04:00
d72c525b46
rfsom: sd1 to sd0 changes
2015-03-19 09:34:14 -04:00
fb5966f9fd
rfsom: sd1 to sd0 changes
2015-03-19 09:34:13 -04:00
6cc8f142f1
rfsom: sd1 to sd0 changes
2015-03-19 09:34:12 -04:00
f0d08abe03
fmcomms2: Fix system_top.v for a few carrier
...
Interrupts are connected inside IPI. Fix system_top for zed, zc702, zc706 and kc705.
2015-03-18 10:37:24 +02:00
72b41c981f
kc705_base: Fix base address overlap
2015-03-18 10:33:17 +02:00
9b6531f79f
ad6676evb: 2014.4 updates
2015-03-17 16:53:13 -04:00
ee89862de9
ad6676evb: 2014.4 updates
2015-03-17 16:53:13 -04:00
1da8356f05
ad6676evb: 2014.4 updates
2015-03-17 16:53:13 -04:00
7456ca67a8
ad6676evb: 2014.4 updates
2015-03-17 16:53:13 -04:00
08a773b92d
fmcomms2/rfsom: interrupt fix
2015-03-17 16:31:12 -04:00
a92c5cb4ff
fmcomms7: 2014.4 updates
2015-03-17 14:01:47 -04:00
18891d036b
fmcomms7: 2014.4 updates
2015-03-17 14:01:47 -04:00
b2e05ce108
fmcomms7: 2014.4 updates
2015-03-17 14:01:47 -04:00
3e73b711e8
fmcomms7: 2014.4 updates
2015-03-17 14:01:47 -04:00
8cb96533d3
fmcomms7: 2014.4 updates
2015-03-17 14:01:46 -04:00
7bdce3837e
fmcomms2: Update interrupts
...
The new interrupts connections are made inside IPI by the process called 'ad_cpu_interrupt'.
2015-03-16 19:13:45 +02:00
65b16551c3
fmcomms2_kc705: Fix system_top connections
2015-03-16 19:12:04 +02:00
cea2d90eb2
base_kc705: Fix different issues
...
+ No more constant block inside IPI.
+ Gpio switch/led is on the axi_gpio first channel.
+ Fix the address map
+ Remove hdmi/spdif related constraints from base constraints
2015-03-16 19:10:57 +02:00
65654b77ff
fmcomms2_kc705: Update design to the new hdl framework
2015-03-13 18:54:28 +02:00
7befef6662
fmcomms2_zed: Update design to the new hdl framework
2015-03-13 18:52:57 +02:00
f7dd466469
adi_board.tcl : Fix some issue with the ad_mem_hpx_interconnect
...
Sometimes the find_bd_objs does not do its job, so need to double check that the interface clock is already connected to the p_clock or not.
Not sure about the cause of this behavior, need more investigation. Issue was found first at KC705 base design.
2015-03-13 18:51:21 +02:00
70e1d13a7b
fmcomms2: Updated project
2015-03-13 12:49:17 +02:00
ea303c6f61
zc702: Updated base design to the latest model
2015-03-13 12:44:08 +02:00
17d8c1b72b
daq2: move intrs into ipi
2015-03-12 16:17:17 -04:00
3a2d1004b5
daq2: move intrs into ipi
2015-03-12 16:17:09 -04:00
b1b46ed820
daq2: move intrs into ipi
2015-03-12 16:17:04 -04:00
ff3dcbc2cb
daq2: move intrs into ipi
2015-03-12 16:16:55 -04:00
8ad8ec4d1e
ml605 removed
2015-03-12 13:00:28 -04:00
e520f5c55a
ad9671_fmc: removed
2015-03-12 12:00:46 -04:00
73680d1ed9
fmcomms2/ml605: removed
2015-03-12 11:59:18 -04:00
18c03a57f8
adv7511/mb: added board files
2015-03-12 11:09:32 -04:00
7f462a1b34
adv7511/mb: added board files
2015-03-12 11:09:27 -04:00
15967f913f
adv7511/mb: added board files
2015-03-12 11:09:20 -04:00
8d0c3573cc
adv7511/kcu105: hdmi/spdif moved out of base design
2015-03-11 15:22:39 -04:00
491b67c13a
adv7511/kcu105: hdmi/spdif moved out of base design
2015-03-11 15:22:39 -04:00
68361bafd4
zc706_base: The FCLK_CLK2 is not used.
2015-03-11 18:10:32 +02:00
a3e73a1837
ad9467_fmc: Fix port names at ILA logic
...
In the version 2014.2 the output port of a constant module was changed from 'const' to 'dout'.
This commit fix the non working ILA.
2015-03-11 14:45:02 +02:00
543bfe9d44
daq2/kcu105: removed hdmi/spdif
2015-03-10 16:15:16 -04:00
ae16aeb064
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:15 -04:00
d7993401e6
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:14 -04:00
09b916d0c7
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:13 -04:00
20b2c19987
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:11 -04:00
ad41d250a8
kcu105/adv7511: moved hdmi/spdif out of base design
2015-03-10 16:15:10 -04:00
1cf8092ba9
fmcomms2/zc706: spi/gpio changes
2015-03-10 16:06:22 -04:00
631c71373a
fmcomms2/zc706: spi/gpio changes
2015-03-10 16:06:18 -04:00
796a0f4f2b
fmcomms2/zc706: spi/gpio changes
2015-03-10 16:06:13 -04:00
8967903d76
zc706: intr sensitivity level-high
2015-03-10 16:05:05 -04:00
7012172f66
fmcomms2: spi/gpio moved to base design
2015-03-10 15:27:32 -04:00
7da65ef3db
fmcomms2: spi/gpio moved to base design
2015-03-10 15:27:28 -04:00
abae36b12f
fmcomms2: spi/gpio moved to base design
2015-03-10 15:27:22 -04:00
9e57e919c4
fmcomms2: spi/gpio moved to base design
2015-03-10 15:26:57 -04:00
a68463d033
rfsom: board updates
2015-03-10 15:26:31 -04:00
e38356b243
rfsom: board updates
2015-03-10 15:26:24 -04:00
c0eef42647
adi_board: enable ps7 hp if needed
2015-03-09 16:12:23 -04:00
59457cb3d4
daq2/zc706: base system updates
2015-03-09 16:10:56 -04:00
ce5ece5494
daq2/zc706: base system updates
2015-03-09 16:09:54 -04:00
104782af87
daq2/kcu105: base system updates
2015-03-09 16:09:07 -04:00
548ae9d39e
daq2: move gpio/spi to base design
2015-03-09 16:08:25 -04:00
f0395b646c
plddr3: ad_connect updates
2015-03-09 16:07:37 -04:00
031dffa80c
zc706: move gpio/spi to base design
2015-03-09 16:07:02 -04:00
2302f282d3
sys_dmafifo: ad_connect updates
2015-03-09 16:06:06 -04:00
545c0baada
kcu105: gpio led/sw merged to bd default
2015-03-09 16:05:28 -04:00
b31d9abd91
kcu105: gpio/spi moved to base design
2015-03-09 16:04:09 -04:00
ed28b47203
board: optimize interconnect for performance
2015-03-06 12:38:52 -05:00
d5eaadd872
daq2: remove ila for kcu105 ddr-300M timing
2015-03-06 12:38:08 -05:00
1db5f4696f
kcu105: isolate ddr-300M from interconnect-100M timing
2015-03-06 12:37:31 -05:00
da5b136f5a
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
0ac1676318
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
7fba7cc6e5
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
af465cbc80
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
1220b53c8c
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
75c4228987
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
605d23d3a4
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
91765fdd82
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
7bf4141a3f
daq2+base: board tcl updates
2015-03-05 10:56:36 -05:00
bf1388b05e
kcu105: rev.d changes
2015-03-04 12:43:04 -05:00
4f918cdce9
2014.4.1 ultrascale updates
2015-02-26 16:10:57 -05:00
847c2e049a
kcu105: removed lutram constraints
2015-02-26 16:09:55 -05:00
1613f7fb41
cftl_cip: Add util_pmod_fmeter IP to library
...
Frequency meter IP for CN0332.
2015-02-23 17:20:12 +02:00
abde4048e0
fmcomms1: Add extra AXI slice on ADC DMA path
...
Add a extra AXI slice on the ADC DMA data path to the HP interconnect to
improve the timing.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-02-20 16:43:45 +01:00
b9d16a7eb1
scripts: renaming board parameters
2015-02-20 09:12:30 -05:00
288f5378ff
rfsom: schematic changes
2015-02-18 14:32:41 -05:00
93e2bcd911
rfsom: schematic changes
2015-02-18 14:32:30 -05:00
383cf3b3a3
rfsom: schematic changes
2015-02-18 14:32:20 -05:00
d2e9b1fe03
rfsom: schematic changes
2015-02-18 14:32:04 -05:00
3113abf038
cftl_cip: Add gpio counter for CN0332
...
Add a counter core to the design, to support the CN0332 pmod with a speed sensor.
Change a naming for the custom cores.
2015-02-18 18:24:46 +02:00
e111e1336e
conflicts-
2015-02-06 22:14:21 -05:00
2d607d765b
cftl_cip: Add a clock input to the device core, for the SPI clock.
...
This clock can be adjustable from the system_project.tcl
2015-02-04 14:55:17 +02:00
996e1b7970
rfsom: constraint updates
2015-02-03 14:20:34 -05:00
fd2ab02174
cftl_std: Added in the constraint file comments regarding supported CFTLs
2015-01-29 16:27:43 +02:00
d69d105b5d
vc707_common: Fix address mapping
...
The axi_ethernet/eth_buf/S_AXI_2TEMAC address space and axi_ethernet/eth_mac/s_axi/Reg address
segment does not exist in 2014.4.
2015-01-29 12:22:06 +02:00
e8ff30119d
vc707_xdc: Delete unnecessary clock definition
2015-01-29 11:39:10 +02:00
6c8ea24f20
common: Update VC707 base design to 2014.4
2015-01-28 16:24:52 +02:00
e1d8dd10a9
daq2: Initial check in of the VC707 based project
...
NOTE: Can not communicate with the clock chip, rx/tx PLL not locking.
2015-01-28 16:24:06 +02:00
659e0cca4e
cftl_cip: Initial check in.
...
Project cftl_cip supports the following Circuits from the Lab pmods:
+ EVAL-CN0350-PMDZ
+ EVAL-CN0335-PMDZ
+ EVAL-CN0336-PMDZ
+ EVAL-CN0337-PMDZ
Note: Additional testing needed!
2015-01-23 18:29:32 +02:00
463a3bbc88
cftl_std: Updated project. Switched to PS7 gpio. Renamed signals.
2015-01-23 14:11:33 +02:00
9672271155
fmcjestadc1: a5gt: Updated project to work with linux and fixed ethernet
...
- added phy reset mechanism for proper functioning of the ethernet
- not all DDR is accesible, as NIOS2 can't access it with MMU enabled
2015-01-23 13:30:56 +02:00
5a77ab0161
a5gt:common: Added phy reset signal from ethernet in pin assignments
2015-01-23 12:31:41 +02:00
050f17e034
a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2
2015-01-23 12:30:16 +02:00
72e89852b6
daq2/kc705: 2014.4 updates
2015-01-14 12:58:08 -05:00
024d9e7309
replace export hardware -- hwdef/sysdef
2015-01-13 13:40:21 -05:00
03988f1c9f
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:20 -05:00
b595cce697
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:18 -05:00
b0b4bfe531
kcu105-daq2-2014.4-- intermediate fixes
2015-01-13 13:40:17 -05:00
47871287f3
kc705: Updated base project with linear flash. Updated all depending projects
2015-01-13 10:19:07 +02:00
b9e2c5659f
fmcomms2: 2014.4
2015-01-09 14:12:54 -05:00
9e64df917c
daq2: 2014.4
2015-01-09 14:12:53 -05:00
65d9f08763
zc706: mig 2014.4
2015-01-09 14:12:52 -05:00
868df1aac8
zc706: mig 2014.4
2015-01-09 14:12:51 -05:00
0258afbadc
board: add ddr seg variable
2015-01-09 14:12:50 -05:00
22d881981e
cftl_std: Renamed cftl standard project
2015-01-09 19:44:13 +02:00
debbe31713
Merge remote-tracking branch 'origin/master' into dev
2015-01-09 11:12:56 -05:00
117686f352
ad9739a: updates for ad9739a
2015-01-09 10:54:50 -05:00
785d3a4ae3
ad9739a: updates for ad9739a
2015-01-09 10:54:40 -05:00
e8d0782a2e
ad9739a: updates for ad9739a
2015-01-09 10:54:22 -05:00
baea2090d6
ad9739a: updates for ad9739a
2015-01-09 10:54:12 -05:00
c9b6411e86
ad9739a: updates for ad9739a
2015-01-09 10:54:00 -05:00
51e6d0888a
cftl_xil_zed: Initial commit for common platform used with CFTL circuits
...
This common platform uses PS7 SPI and I2C to communicate with different chips.
On different connectors different pin configurations are supported:
- On connector JA, a spi interface and a 2 pin GPIO
- On connector JB, a I2C interface
- On connector JC, a spi interface with 2 chip selects
2015-01-09 17:47:29 +02:00
a9cc8f6c91
ad9739a_fmc: added
2015-01-08 10:35:59 -05:00
a170ebfb82
imageon: Initial commit
...
Initial commit of the IMAGEON project for ZC706. NOT tested.
2015-01-08 17:01:22 +02:00
f566268db5
zed_common: Updated common to 2014.4
2015-01-08 11:59:26 +02:00
f6df66ea06
motcon2_fmc: initial commit of the base design
...
Because vivado crashes when adding the speed detector, it's not part of this commit.
The controller is also not part of this commit
2015-01-08 11:57:22 +02:00
eb569b991d
dmafifo- remove util fifo setup
2015-01-06 16:23:14 -05:00
9e707d8a33
rfifo: wrapper updates
2015-01-06 16:17:33 -05:00
a944deebd5
wfifo: wrapper updates
2015-01-06 16:17:25 -05:00
d2baf17ff0
rfsom: updated to rfsom
2014-12-23 14:04:02 -05:00
3d1ba585ee
rfsom: updated to rfsom
2014-12-23 14:04:01 -05:00
19c2da836c
rfsom: updated to rfsom
2014-12-23 14:03:59 -05:00
61ba4f4357
rfsom: updated to rfsom
2014-12-23 14:03:58 -05:00
614dfcd93c
rfsom: updated to rfsom
2014-12-23 14:03:57 -05:00
4b571ded8f
fmcomms2/rfsom: initial commit
2014-12-23 14:03:56 -05:00
ee52602c89
rfsom: initial commit
2014-12-23 14:03:55 -05:00
8e41af7b92
fmcomms2: 2014.4 update
2014-12-23 14:03:54 -05:00
0de1a38245
zc706: 2014.4 update
2014-12-23 14:03:52 -05:00
43037a42eb
scripts: 2014.4 update
2014-12-23 14:03:51 -05:00
71baa129a7
VC707: Fixed linear flash timings
2014-12-19 15:45:14 +02:00
2ff72d60d1
fmcomms2: Updated VC707 project to fix ethernet problem
2014-12-19 15:45:05 +02:00
4a9c4cdf19
fmcadc2_zc706: Fix PLDDR fifo name
2014-12-19 13:01:33 +02:00
6230cb25b7
fmcomms7_zc706: Add constraint file for PLDDR
2014-12-19 13:01:27 +02:00
6e124c4c24
fmcomms7_zc706: Connect PLDDR rst to external push button
2014-12-19 13:01:21 +02:00
a0b83bac7f
fmcomms7_zc706: Delete trailing spaces from system top
2014-12-19 13:01:15 +02:00
362b0f5300
daq3_zc706: Add constraint file for PLDDR
2014-12-19 13:01:10 +02:00
d77e28e372
daq3_zc706: Connect PLDDR rst to external push button
2014-12-19 13:01:05 +02:00
d483801e2d
daq3_zc706: Delete trailing spaces from system_top
2014-12-19 13:00:59 +02:00
df205f5cea
fmcadc2_zc706: Connect PLDDR rst to external push button
2014-12-19 13:00:53 +02:00
8fc1f046a4
fmcadc4_zc706: Add constraint file for PLDDR
2014-12-19 13:00:48 +02:00
7ec1e282d9
daq2_zc706: Add constraint file for the PLDDR
2014-12-19 13:00:42 +02:00
a6cf615ee0
zc706_constr: Move the sys_rst related constraint definition to zc706_system_mig_constr.xdc
2014-12-19 13:00:35 +02:00
153a4cef18
daq2: missing sys_rst decl.
2014-12-19 13:00:21 +02:00
ad144ef06a
plddr3: sys-rst from board pushbutton
2014-12-19 13:00:07 +02:00
33a8c8a155
plddr3: sys-rst from board pushbutton
2014-12-19 13:00:01 +02:00
0cc29fe03b
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:54 +02:00
51bdcb1b12
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:48 +02:00
daba3fb72e
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:42 +02:00
758ac6bb8e
plddr3: sys-rst from board pushbutton
2014-12-19 12:59:35 +02:00
1a9eb8196a
VC707: Fixed linear flash timings
2014-12-18 17:49:00 +02:00
23e2886b5d
fmcadc2_zc706: Fix PLDDR fifo name
2014-12-18 16:57:19 +02:00
b684c8bf33
fmcomms7_zc706: Add constraint file for PLDDR
2014-12-18 10:15:11 +02:00
ae09030044
fmcomms7_zc706: Connect PLDDR rst to external push button
2014-12-18 10:14:32 +02:00
0aa4661122
fmcomms7_zc706: Delete trailing spaces from system top
2014-12-18 10:13:16 +02:00
e81327b794
daq3_zc706: Add constraint file for PLDDR
2014-12-18 10:08:33 +02:00
8121d11993
daq3_zc706: Connect PLDDR rst to external push button
2014-12-18 10:07:52 +02:00
090aed508e
daq3_zc706: Delete trailing spaces from system_top
2014-12-18 10:06:29 +02:00
abdb59a28e
fmcadc2_zc706: Connect PLDDR rst to external push button
2014-12-18 10:04:01 +02:00
31a95042cf
fmcadc4_zc706: Add constraint file for PLDDR
2014-12-18 10:01:16 +02:00
39cc7b8b2e
daq2_zc706: Add constraint file for the PLDDR
2014-12-18 10:00:35 +02:00
59e610be09
zc706_constr: Move the sys_rst related constraint definition to zc706_system_mig_constr.xdc
2014-12-17 19:07:43 +02:00
656246f2ba
fmcomms2: Updated VC707 project to fix ethernet problem
2014-12-17 16:16:01 +02:00
90fe993db2
daq2: missing sys_rst decl.
2014-12-15 14:39:40 -05:00
725b407523
plddr3: sys-rst from board pushbutton
2014-12-15 12:59:36 -05:00
7b1e3d77e8
plddr3: sys-rst from board pushbutton
2014-12-15 12:59:25 -05:00
0a6769fda9
plddr3: sys-rst from board pushbutton
2014-12-15 12:59:16 -05:00
f99bd3609b
plddr3: sys-rst from board pushbutton
2014-12-15 12:59:04 -05:00
77fa96fa67
plddr3: sys-rst from board pushbutton
2014-12-15 12:58:54 -05:00
ed7f8b4908
plddr3: sys-rst from board pushbutton
2014-12-15 12:58:44 -05:00
ca36ef0e02
Merge remote-tracking branch 'origin/hdl_2014_r2' into dev
2014-12-11 11:26:30 -05:00
d82952b22a
daq2/kcu105: lane assignment fixes
2014-12-11 11:19:38 -05:00
7dddac84f1
motcon1_fmc: Fixed issue introduced by merge
2014-12-11 14:32:32 +02:00
9e8fd8ed9e
base_design: External IIC reset is connected to Vcc
...
External IIC reset is connected to Vcc in case of AC701, KC705 and VC707
2014-12-11 11:14:54 +02:00
caa0268434
base_design: External IIC reset is connected to Vcc
...
External IIC reset is connected to Vcc in case of AC701, KC705 and VC707
2014-12-11 11:13:07 +02:00
86ad9213e0
fmcomms2: Update c5soc system_timing script
2014-12-10 17:54:11 +02:00
6ac774a9dd
fmcjesdadc1: Update altera system_timing script
2014-12-10 17:53:29 +02:00
e7c920bbd9
fmcomms2/ml605: compilation fixes
2014-12-09 14:32:39 -05:00
4cf435ee39
fmcomms2/ml605: compilation fixes
2014-12-09 14:32:39 -05:00
8b41034825
fmcomms2/ml605: compilation fixes
2014-12-09 14:32:39 -05:00
842ba19aaa
fmcomms2/ml605: compilation fixes
2014-12-09 14:31:12 -05:00
d7a6b5e6d0
fmcomms2/ml605: compilation fixes
2014-12-09 14:31:11 -05:00
d57b6b01c6
fmcomms2/ml605: compilation fixes
2014-12-09 14:31:10 -05:00
9103f6706e
Merge branch 'hdl_2014_r2' of https://github.com/analogdevicesinc/hdl into hdl_2014_r2
2014-12-09 17:38:37 +01:00
138e789fb6
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl: Fix interrupts
...
sys_concat_intc: don't reset NUM_PORTS to 6
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-09 17:38:16 +01:00
772edbae20
fmcadc4: fifo updates
2014-12-09 10:43:02 -05:00
d149890426
fmcadc4: fifo updates
2014-12-09 10:43:02 -05:00
dad0745fbe
fmcadc4: fifo updates
2014-12-09 10:43:02 -05:00
987257e3c3
fmcadc4: fifo updates
2014-12-09 10:43:01 -05:00
0c6cbdd303
fmcadc4: fifo updates
2014-12-09 10:38:51 -05:00
f044ab94e0
fmcadc4: fifo updates
2014-12-09 10:38:50 -05:00
e2a9502e1e
fmcadc4: fifo updates
2014-12-09 10:38:49 -05:00
a2607a8057
fmcadc4: fifo updates
2014-12-09 10:38:47 -05:00
a6b7b9d880
ad9467_kc705: Fix memory segment offset for SEG_axi_ddr_cntrl
2014-12-09 16:20:39 +02:00
2e4640d5c5
ad9467_kc705: Fix memory segment offset for SEG_axi_ddr_cntrl
2014-12-09 16:17:46 +02:00
4d28825741
ad9467_kc705: Fix typos.
2014-12-09 13:46:51 +02:00
a0d5e7862e
ad9467_kc705: Fix typos.
2014-12-09 12:07:49 +02:00
915ee7a268
fmcjesdadc1_kc705: Connect the SPI interrupt to the controller
2014-12-09 11:54:16 +02:00
ee04eb637b
ad9467_kc705: Fix interrupts
2014-12-09 11:54:08 +02:00
37c3af9929
fmcjesdadc1_kc705: Connect the SPI interrupt to the controller
2014-12-09 11:51:36 +02:00
b83299c606
ad9467_kc705: Fix interrupts
2014-12-09 11:48:46 +02:00
1b4a4bc06e
daq3: compilation fixes - latest changes
2014-12-08 14:51:52 -05:00
c0d588ba8c
daq3: compilation fixes - latest changes
2014-12-08 14:51:52 -05:00
26d72d306e
daq3: compilation fixes - latest changes
2014-12-08 14:51:51 -05:00
abff7097f6
daq3: compilation fixes - latest changes
2014-12-08 14:50:03 -05:00
8a72a6a0dc
daq3: compilation fixes - latest changes
2014-12-08 14:49:52 -05:00
7c3ed75b79
daq3: compilation fixes - latest changes
2014-12-08 14:49:40 -05:00
0a8fabe874
Merge branch 'hdl_2014_r2' into dev
...
Conflicts:
projects/fmcadc5/common/fmcadc5_bd.tcl
projects/motcon1_fmc/common/motcon1_fmc_bd.tcl
projects/motcon1_fmc/zed/system_constr.xdc
projects/motcon1_fmc/zed/system_top.v
2014-12-08 11:32:13 -05:00
82b9ebe23d
remove replaced projects
2014-12-08 10:45:12 -05:00
19e4950b72
renamed to match official names
2014-12-08 10:44:15 -05:00
a558d4000d
motcon1_fmc: Added XADC to the project, the external muxing is controlled by generic GPIO, not XADC GPIO
2014-12-08 11:27:47 +02:00
d5572eaa49
ad9265_fmc: Fix unconnected DMA irq
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-12-05 17:44:47 +01:00
84174460bb
projects/common/kcu105/kcu105_system_bd: Restore axi_ethernet SupportLevel 0
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:50:45 +01:00
bb6cc40902
projects/common: KCU105 VC707 update and sync axi_ethernet:6.1 features
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:50:45 +01:00
8e4d0a1b60
projects/common: KCU105 VC707 KC705 sync microblaze core defaults
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:50:45 +01:00
7e18162632
projects/common/kcu105/kcu105_system_bd: Restore axi_ethernet SupportLevel 0
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-05 14:48:37 +01:00
e6e9c0058d
motor_control: Updated project to Vivado 14.2. Temporary removed XADC
...
- fixed constraints
- updated interrupt system
- used ad_iobuf
- The XADC was removed because the XADC IPI generates vaux inputs 0 and 10 even if 0 and 8 are selected
2014-12-05 11:53:23 +02:00
4c05e8de5d
motor_control: Updated project to Vivado 14.2. Temporary removed XADC
...
- fixed constraints
- updated interrupt system
- used ad_iobuf
- The XADC was removed because the XADC IPI generates vaux inputs 0 and 10 even if 0 and 8 are selected
2014-12-05 11:48:00 +02:00
11f41d1dff
zynq_plddr3: Fix PLDDR3's Reset Generator
...
Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset.
Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to
set this two property of the reset generator.
2014-12-04 15:42:28 +02:00
34ffa15b12
zynq_plddr3: Fix PLDDR3's Reset Generator
...
Reset generator's external reset signal was active low, but the GT reset is active high, and both the DDR controller and FIFO2S were in reset.
Therefore the external reset active state is changed to active high. This setup in general is made by the tool automatically, in order to do it correctly, need to
set this two property of the reset generator.
2014-12-04 15:39:17 +02:00
58bc7c6886
fmcomms6: Add DMA overflow signal to ILA
...
This is useful for debugging DMA overflows.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-04 14:23:09 +01:00
a9c6148570
fmcomms6: Better cope with higher sample rates
...
There can be a rather high latency between the last byte of a burst has been send and the time the response for the burst is received. Running at high samplerates this can cause the internal DMA store and forward FIFO to fill up and subsequently stall the DMA pipeline and drop samples. To better cope with the situation double the size of the internal FIFO. Also increase the clock of the AXI bus to be able to accommodate a samplerate of 310MHz.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-04 13:56:59 +01:00
324c0528c2
fmcomms6: Better cope with higher sample rates
...
There can be a rather high latency between the last byte of a burst has been send and the time the response for the burst is received. Running at high samplerates this can cause the internal DMA store and forward FIFO to fill up and subsequently stall the DMA pipeline and drop samples. To better cope with the situation double the size of the internal FIFO. Also increase the clock of the AXI bus to be able to accommodate a samplerate of 310MHz.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-04 13:28:37 +01:00
46156b7ceb
fmcomms6: Add DMA overflow signal to ILA
...
This is useful for debugging DMA overflows.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-04 13:28:37 +01:00
3cc890e604
projects/common: KCU105 VC707 update and sync axi_ethernet:6.1 features
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-04 09:49:09 +01:00
2d8450abc4
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-12-04 09:47:46 +01:00
3bc9b25e96
projects/common: KCU105 VC707 KC705 sync microblaze core defaults
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-12-04 09:47:02 +01:00
56a8a54080
ad9625x2_fmc: Increase the dma fifo data depth
2014-12-03 12:13:08 +02:00
757c213165
ad9625x2_fmc: Integrate the dac spi interface into the SPI interface
2014-12-03 12:06:43 +02:00
48673fec6a
ad9625x2_fmc: Integrate the dac spi interface into the SPI interface
2014-12-03 12:01:47 +02:00
80d1314c5e
ad9625x2_fmc: Reverse "Add a separate SPI for the DAC interface"
2014-12-03 10:14:09 +02:00
d89ed56e10
ad9625x2_fmc: Increase the data depth of the dmafifo
2014-12-02 19:29:19 +02:00
0007054638
ad9625x2_fmc: Add a separate SPI for the DAC interface
...
DAC spi interface is controlled by an axi_spi core.
Modifications on GPIO layout: pwr_good is 12, vdither 13 and trig is 14.
2014-12-02 19:29:18 +02:00
805d52346c
fmcomms7: compilation fixes on plddr3
2014-12-02 10:39:01 -05:00
f01d1aae2d
fmcomms7: compilation fixes on plddr3
2014-12-02 10:38:44 -05:00
95e113e1a3
fmcomms6: Connect DMA directly to the HP port
...
The axi_dmac supports native AXI3, there is no need to add a interconnect
for protocol conversion between it and the HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:45:45 +01:00
45fc7bb7e2
fmcomms6: Set ila type to native
...
With version 4.0 ila defaults to the AXI monitor type, so explicitly
configure it for native.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:45:45 +01:00
5b68b79dec
ad9467_fmc: Set ila type to native
...
With version 4.0 ila defaults to the AXI monitor type, so explicitly
configure it for native.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:45:45 +01:00
d773673e4f
fmcomms6: Connect DMA directly to the HP port
...
The axi_dmac supports native AXI3, there is no need to add a interconnect
for protocol conversion between it and the HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:44:09 +01:00
5169d3ef59
fmcomms6: Set ila type to native
...
With version 4.0 ila defaults to the AXI monitor type, so explicitly
configure it for native.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:44:09 +01:00
3c85c7e2f8
ad9467_fmc: Set ila type to native
...
With version 4.0 ila defaults to the AXI monitor type, so explicitly
configure it for native.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-12-01 13:44:08 +01:00
7a55db59f6
fmcomms2: Zed, fixed iic multiplexer ad_iobuf connections
2014-11-28 14:19:08 +02:00
d5422c2ecc
fmcomms2: Zed, fixed iic multiplexer ad_iobuf connections
2014-11-28 14:17:09 +02:00
d5a1df2fe6
usdrx1_zc706: Update interrupts.
2014-11-27 14:06:13 +02:00
eed1981ede
usdrx1_fmc: Fix GT lane number definition.
2014-11-27 14:05:54 +02:00
a576f7dc98
ad9671_zc706: Update interrupts
2014-11-27 14:05:43 +02:00
0ccc546aeb
ad9671_fmc: Fix GT lane number definition
2014-11-27 14:05:34 +02:00
ee7d427123
ad9671_fmc: Cosmetic changes
...
Delete trailing whitespaces.
2014-11-27 14:05:24 +02:00
4ea86de4db
usdrx1_zc706: Update interrupts.
2014-11-27 14:03:54 +02:00
d1af4d2951
usdrx1_fmc: Fix GT lane number definition.
2014-11-27 14:03:10 +02:00
82561b48cc
ad9671_zc706: Update interrupts
2014-11-27 14:02:18 +02:00
92f85086e3
ad9671_fmc: Fix GT lane number definition
2014-11-27 14:01:36 +02:00
98e8f21c1d
ad9671_fmc: Cosmetic changes
...
Delete trailing whitespaces.
2014-11-27 14:00:35 +02:00
419d38b9f6
kc705_base: Define sys_addr_mem_seg for dmafifo
2014-11-26 15:38:41 +02:00
6fd2f8c913
daq2_fmc: Update interrupts
...
Update interrupts for ZC706 and KC705 carrier.
2014-11-26 15:38:24 +02:00
bfd89dc9c7
daq2_kc705: Fix constraint file
...
I/O standard for trig_[p/n] is LVDS_25
2014-11-26 15:38:10 +02:00
630f26442a
daq2_kc705: Instantiate dmafifo module
2014-11-26 15:37:57 +02:00
00c7b23b21
daq2_fmc: Cosmetic changes
...
Delete trailing whitespaces, no functional changes.
2014-11-26 15:37:48 +02:00
12f1873e17
kc705_base: Define sys_addr_mem_seg for dmafifo
2014-11-26 15:08:55 +02:00
8dad54b6e3
daq2_fmc: Update interrupts
...
Update interrupts for ZC706 and KC705 carrier.
2014-11-26 13:53:18 +02:00
4b6968c2af
daq2_kc705: Fix constraint file
...
I/O standard for trig_[p/n] is LVDS_25
2014-11-26 13:51:46 +02:00
14193cf4bd
daq2_kc705: Instantiate dmafifo module
2014-11-26 13:50:42 +02:00
f28845cc0d
daq2_fmc: Cosmetic changes
...
Delete trailing whitespaces, no functional changes.
2014-11-26 13:48:48 +02:00
199e86d715
fmcomms2: Added iic_fmc_intr to the zed top file
2014-11-26 11:47:16 +02:00
03751827cb
fmcomms2: Updated vc707 project
...
- updated constraints
- updated interrupts
- used ad_iobuf
- added linear_flash
2014-11-26 11:47:06 +02:00
40c5816bd7
fmcomms2: Updated mitx045 project. Updated constraints. Updated interrupts
2014-11-26 11:46:53 +02:00
84052ad437
Add Vivado version check to adi_project_create
...
The scripts generating the projects files typically only work correctly with
one specific version of Vivado. If a incorrect version is used the script
may fail at some point with a cryptic error message or may not fail but
create a bitstream that is not working as expected, e.g. unconnected
signals, etc. This patch adds a version check to adi_project_create that
will error out early on stating that the wrong version of Vivado was used
and which is the right version to use.
By default the required version will be the version that is required by the
common scripts. Individual projects can overwrite the required version by
setting the REQUIRED_VIVADO_VERSION variable to the required version or can
bypass the version check completely by setting the IGNORE_VERSION_CHECK
variable to 1.
Callers of the script can also disable the version check by setting the
ADI_IGNORE_VERSION_CHECK environment variable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-11-26 10:46:34 +01:00
303a2683a2
fmcomms2: Added iic_fmc_intr to the zed top file
2014-11-26 11:26:58 +02:00
6227bc82c0
fmcomms2: Updated vc707 project
...
- updated constraints
- updated interrupts
- used ad_iobuf
- added linear_flash
2014-11-26 11:25:19 +02:00
2f77daf71d
fmcomms2: Updated mitx045 project. Updated constraints. Updated interrupts
2014-11-26 11:21:20 +02:00
626b719ad8
ad6676ebv_vc707: Update the interrupts
2014-11-26 10:56:47 +02:00
322324b891
ad6676evb_vc707: Add support for linear flash
2014-11-26 10:56:36 +02:00
67f82c9e3e
ad6676_fmc: Fix GT lane number definition
2014-11-26 10:56:23 +02:00
5e70ef4ab9
ad6676ebv_vc707: Update the interrupts
2014-11-26 10:49:14 +02:00
72f9dd226a
ad6676evb_vc707: Add support for linear flash
2014-11-26 10:48:27 +02:00
d75487d0a2
ad6676_fmc: Fix GT lane number definition
2014-11-26 10:45:00 +02:00
81f0e417d4
Add Vivado version check to adi_project_create
...
The scripts generating the projects files typically only work correctly with
one specific version of Vivado. If a incorrect version is used the script
may fail at some point with a cryptic error message or may not fail but
create a bitstream that is not working as expected, e.g. unconnected
signals, etc. This patch adds a version check to adi_project_create that
will error out early on stating that the wrong version of Vivado was used
and which is the right version to use.
By default the required version will be the version that is required by the
common scripts. Individual projects can overwrite the required version by
setting the REQUIRED_VIVADO_VERSION variable to the required version or can
bypass the version check completely by setting the IGNORE_VERSION_CHECK
variable to 1.
Callers of the script can also disable the version check by setting the
ADI_IGNORE_VERSION_CHECK environment variable.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-11-25 18:35:11 +01:00
2e72a2cc0c
fmcomms1: Updated VC707 project with latest interrupts and linear flash. Fixed constraints and constraint priority
2014-11-25 15:00:00 +02:00
dbc9da8598
fmcomms1: Updated KC705 project with latest interrupts. Fixed constraints and constraint priority
2014-11-25 14:56:22 +02:00
87324d8a14
fmcomms1: Updated AC701 project with latest interrupts. Fixed constraints and constraint priority
2014-11-25 14:54:01 +02:00
b8ab2ff847
fmcomms1: updated common project
...
- increased the DMA FIFOs to 64
- added axi slices to the source and destination for DMAs
- for microblaze systems, increade the ad9643 dma data width at destination
- removed sys_fmc_dma_clk and used the sys_200m_clk instead for DMA data transfer
2014-11-25 14:51:42 +02:00
2bd154ad59
xfest14_zed: Update project to 2014.2
2014-11-25 12:53:42 +02:00
a1e67a5912
ad9625x2_fmc: dmafifo address width now is an argument of the process
2014-11-24 19:22:18 +02:00
660424ef99
fmcomms6_fmc: Update interrupts
2014-11-24 18:23:35 +02:00
56aefb62ed
fmcomms6_fmc: Cosmetic changes
...
Delete trailing white spaces, and fix alignment.
2014-11-24 18:23:34 +02:00
68ac015825
daq1_fmcl: Fix GT lane number definitions
...
Update which fix issues caused by GT lane number parameters change. (commit f8e7796592
2014-11-24 18:23:33 +02:00
0ecfc14e95
daq1_fmc: Update interrupts.
2014-11-24 18:23:32 +02:00
9b104f1657
daq1_fmc: Get rid of the concat module inside the block design.
...
xl_concat just causing troubles, no need to use it, if not justified.
2014-11-24 18:23:30 +02:00
64b4d0177e
ad9467_zed: Using ad_iobuf module for IO buffer instantiations on top
...
No functional changes, we just try to keep consistency.
2014-11-24 18:23:29 +02:00
83c2eefea2
ad9467_fmc: Update interrupts
2014-11-24 18:23:28 +02:00
114406335d
ad9467_fmc: Connect dma controller directly to the HP port
2014-11-24 18:23:27 +02:00
67065a3130
ad9680_eval: removed
2014-11-24 11:04:34 -05:00
76fb5d3da9
ad9625_vc707: dmafifo address width now is an argument of the process
2014-11-24 16:52:10 +02:00
1834cf6d38
adi_prcfg_project: Update the PR design flow
...
Optimization directive kept on default in the implementation flow.
2014-11-21 19:26:33 +02:00
83d79a6acf
fmcomms2_pr: Update system_project script for mitx
...
Bist logic is using the pnmon module for PRBS checking.
2014-11-21 19:23:12 +02:00
6517a94929
fmcomms2_pr: Update interrupts and iobuf
...
No functional changes, update to the new interrupt path, and change the
iobuf instantiation in order to keep consistency.
2014-11-21 19:22:03 +02:00
65588f1b67
fmcomms2_pr: Cosmetic changes of mitx system top.
2014-11-21 19:20:30 +02:00
84f8377beb
fmcjedadc1_vc707: Add support for linear flash interface
2014-11-21 19:19:21 +02:00
e8546b9c3b
fmcjesdadc1: Update interrupts for KC705 and VC707
2014-11-21 19:18:30 +02:00
b0f571ce0c
fmcjesdadc1: Fix parameter lane number for GT core
2014-11-21 19:17:29 +02:00
c0f4d7e2b5
mitx045_common: Definition file patch
...
In 2014.2 tool version, the way how a definition file needs to be applied is different
The command "apply_bd_automation" should be used, instead setting property PCW_IMPORT_BOARD_PRESET
In non-project mode (PR design flow), after creating the static design the type of the board is set.
NOTE: the definition file for mitx must be installed accordingly in order to get this work
See link: http://zedboard.org/support/documentation/2056
2014-11-21 19:14:37 +02:00
5e08e18022
ad9434_fmc: Update interrupts
2014-11-21 19:06:48 +02:00
db004641d3
kcu105: dmafifo address width change
2014-11-20 09:28:03 -05:00
cdd1408d3c
dmafifo: parameterized address width
2014-11-20 09:28:02 -05:00
2912372d6e
ad9625_fmc: Add support for AD-JESDCLOCK1-EBZ
...
Connect the SPARE_CLOCK_DUT pin to GPIO, this will be used to reset the AD9527.
The SPI interface for the clock chip is already integrated into the design.
2014-11-18 14:11:51 +02:00
bbf1f0c156
adi_project: Add board definition for mitx045
2014-11-18 10:05:57 +02:00
e3378cd6cb
mitx045_board_definition: revert old board definition file
...
Revert commit 4f6aa159b8
2014-11-18 10:05:55 +02:00
6e194dbcc0
adv7511_ac701: Fix project source files definition
2014-11-18 10:05:54 +02:00
766589637e
prcfg_zc706: Update data width and project script
2014-11-18 10:05:53 +02:00
5c7e8eb926
prcfg_setup: Fix data width, delete invalid ILA configurations
2014-11-18 10:05:51 +02:00
bd57c2246e
prcfg: Increase the PR portion area in order to increase the DSP resource.
2014-11-18 10:05:49 +02:00
344f1bb539
adv7511_kc705: Fix project source definition
2014-11-18 10:05:48 +02:00
01b3495a81
fmcomms1: Updated ZC706 project to be compatible with util_wfifo and increased system_constr.xdc priority
2014-11-17 18:33:21 +02:00
20a3f322e7
fmcomms1: Updated zc702 project
...
- fixed timing constraints, increased system_constr.xdc priority
- used ad_iobuf
- updated interrupt system to latest implementation
2014-11-17 18:32:12 +02:00
adcd16d033
fmcomms1: Updated zed project
...
- fixed timing constraints
- used ad_iobuf
- updated interrupt system to latest implementation
2014-11-17 18:31:24 +02:00
5d1a0a14bf
ad9625x2_fmc: dma fifo changes
2014-11-14 16:00:32 -05:00
2eb80715e3
ad9625_fmc: dma fifo changes
2014-11-13 14:13:00 -05:00
eaacd4d49a
adi_project.tcl: Fix message severity (working solution)
...
Need to define the default/initial severity too.
2014-11-13 18:55:43 +02:00
4bcf338e9b
adi_project.tcl : Fix message severity
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When message severity is set to 'error', need to do it quiet, other way the tool will stop after synthesis, complaining for previous errors.
2014-11-13 16:33:47 +02:00
5baa015246
kc705_base: Delete timing constraints
2014-11-13 16:30:37 +02:00
3915f7d5f4
daq2: kcu105 dma-fifo changes
2014-11-12 15:25:13 -05:00
d79e95b774
daq2: dma-fifo changes
2014-11-12 15:24:54 -05:00
074662a622
dmafifo: common interface with fifo2s
2014-11-12 15:24:31 -05:00
855919ee8e
plddr3: internal buswidth/clock conversion
2014-11-12 14:43:50 -05:00
dbf5acde76
plddr3: internal buswidth/clock conversion
2014-11-12 14:43:49 -05:00
c6af2696b3
plddr3: internal buswidth/clock conversion
2014-11-12 14:43:48 -05:00
ce92d49565
adv7511: Updated VC707 project to include linear flash
2014-11-12 11:46:01 +02:00
897f5e219d
ad9625_zc706: Update GT configuration
2014-11-11 19:25:30 +02:00
776a396141
adi_project.tcl: Add new message severity definition
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Set "Parameter does not exist!" message severity to error.
2014-11-11 19:20:40 +02:00
8147fa0eb6
fmcomms7: asymmetric no of lanes
2014-11-11 08:54:27 -05:00
439cbecf7c
fmcomms7: asymmetric no of lanes
2014-11-11 08:54:26 -05:00
b96a8d01c3
fmcomms7: asymmetric no of lanes
2014-11-11 08:54:25 -05:00
97fa063341
fmcadc3: Fix pre-processing of ADC data
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-11 11:49:40 +01:00
4ccece5c8d
fmcadc3: Add a chip-select decoder to support up to 7 devices
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This is required for the fmcadc3 board as it features 7 chips all
connected to the same SPI bus (ad9528, ad9234 x2, ada4961 x4).
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-11 11:49:40 +01:00
05ed98f884
common: Updated common constratins for ac701, kc705, vc707, zc702
2014-11-11 12:35:44 +02:00
c1268f089d
scripts: hp/mem updates
2014-11-10 15:06:20 -05:00
3211964c2e
ad6676evb: added
2014-11-10 13:41:01 -05:00
4c0d053055
fmcomms7: compilation fixes
2014-11-10 13:26:28 -05:00
b85c552e43
fmcomms7: constraint updates
2014-11-10 13:26:27 -05:00
87000d7a23
fmcomms7: board updates
2014-11-10 13:26:26 -05:00
82048866dd
fmcomms7: initial updates
2014-11-10 13:26:25 -05:00
c72a04cecf
fmcomms7: initial updates
2014-11-10 13:26:24 -05:00
4d915d539f
fmcomms7: initial updates
2014-11-10 13:26:23 -05:00
0560bd5f99
fmcomms7: initial updates
2014-11-10 13:26:21 -05:00
cbcdf4a2aa
fmcomms7: initial updates
2014-11-10 13:26:20 -05:00
1edef2b8ff
fmcomms7: initial updates
2014-11-10 13:26:19 -05:00
12896c7624
fmcomms7: daq2 copy
2014-11-10 13:26:18 -05:00
50ce2e30be
daq2: ila changes for kcu105 timing
2014-11-10 10:57:35 -05:00
1d73adcbc4
fmcadc3: zc706: Allow to enable pairs of channels and sign-extend data
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-07 18:09:00 +01:00
c33d3dd0af
fmcadc3: zc706: Connect DMA interrupt line
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Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-07 18:08:24 +01:00
ad08c62b36
fmcomms2: Updated zc702 project. Updated interrupts. Updated constraints
2014-11-07 14:01:55 +02:00
4e11e39956
fmcomms2: Updated zed project
...
- Updated interrupt system to the latest implementation
- Fixed constraints
2014-11-07 13:59:46 +02:00
962df53946
fmcomms2: Updated kc705 project to vivado 2014.2.
...
- Updated interrupt system to the latest implementation
- Fixed constraints
- Used ad_iobuf
2014-11-07 13:58:40 +02:00
db18ed4af2
fmcomms2: Updated ac701 project to vivado 2014.2.
...
- Updated interrupt system to the latest implementation
- Fixed constraints
- Used ad_iobuf
2014-11-07 13:56:00 +02:00
7e2a9ce569
fmcomms2: Updated base design interrupt system for microblaze
2014-11-07 13:54:43 +02:00
0ade2a5f67
fmcomms5: Updated project to vivado 2014.2. Updated interrupt system. Fixed constraints
2014-11-07 13:45:15 +02:00
2d9a529ab8
kcu105: ddr - 800M
2014-11-06 16:50:37 -05:00
abad8ddc28
ad9625x2: fix ila connection
2014-11-06 14:22:46 -05:00
a2a2552c60
ad9625_vc707: Update project to support linear flash interface
2014-11-06 15:01:58 +02:00
d55ddc4da5
ad9625_vc707: Delete SEG_axi_bram_ctl_mem memory segment
2014-11-06 15:01:12 +02:00
0ffb1095d9
Revert "ad9625_vc707: Fix source file definition"
...
This reverts commit 6c80d88a0c
2014-11-06 14:59:08 +02:00
6b7fccf56b
ad9625_fmc: Preserve the IRQ layout
2014-11-06 12:20:26 +02:00
0425202da5
fmcadc3: compilation fixes
2014-11-05 11:59:10 -05:00
fcd015305c
ad9625x2_fmc: Updated vc707 project to include linear flash
2014-11-05 17:19:35 +02:00
4634a4f868
vc707: Added linear flash to the base design
2014-11-05 17:18:40 +02:00
f1c5173a12
motor_control: Renamed the project to motcon1_fmc
2014-11-05 09:51:18 +02:00
0f1bc27e27
fmcadc3: Connect adc_dwr and dma_ready to ILAs
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Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-04 18:09:30 +01:00
d7ba7a95a6
fmcadc3: Update to use latest DDR3_fifo IP
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Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-04 18:09:30 +01:00
6c80d88a0c
ad9625_vc707: Fix source file definition
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The project using "p_sys_dmafifo" process, from sys_axi_dmafifo.tcl.
2014-11-04 15:21:25 +02:00
80646a641b
ad9625x2_fmc: constraints order changes
2014-11-03 15:02:35 -05:00
56e65f5926
ad9625x2_fmc: add dma fifo
2014-11-03 15:02:00 -05:00
8c0782cb74
ad9625x2_fmc: constraints changes
2014-11-03 15:01:40 -05:00
beee377fb7
ad9625x2_fmc: interrupts fix
2014-11-03 15:01:15 -05:00
8e6cb2bad4
ad9625x2_fmc: dma fifo additions
2014-11-03 15:00:51 -05:00
7ad9340992
pmod_ad7175: Connect gain control pin
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Connect the gain control pin to GPIO32 of the ZYNQ.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-11-03 15:00:02 +01:00
4eea04cc9d
fmcadc3: zc706: Fix DMA enable connection
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-11-03 14:45:16 +01:00
57137df018
fmcjesdadc1_zc706: Interrupt update
2014-11-03 13:02:09 +02:00
4f815b99a1
kc705_base: Fix sys_concat_intc input connections
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All the unused input pins need to be connected to ground.
2014-11-03 13:02:08 +02:00
8ef3eada7d
adv7511_ac701: Interrupt update
2014-11-03 13:02:07 +02:00
98b92c4bc1
adv7511_kc705: Interrupt update
2014-11-03 13:02:06 +02:00
0246a40e28
adv7511_vc707: Interrupt update
2014-11-03 13:02:05 +02:00
f7588131da
ac701_base: Interrupt update
2014-11-03 13:02:04 +02:00
b92636c6eb
kc705_base: Interrupt update
2014-11-03 13:02:03 +02:00
25f37ffce7
usdrx1: Added cpld configuration files
2014-11-03 12:54:54 +02:00
99ad286c41
kcu105: adv7511 updates
2014-10-31 13:28:17 -04:00
8ed9d10502
ad9625_fmc: disable sync
2014-10-31 13:05:18 -04:00
6f5a268909
fmcomms1: ZC706, updated project with latest constraints and interrupts
2014-10-31 17:59:56 +02:00
a84397d345
motor_control: Changed the encoder pins mapping.
2014-10-31 17:37:28 +02:00
356e1c7ac1
motor_control: Changed the encoder pins mapping.
2014-10-31 17:08:18 +02:00
3c78d8fe58
ad9265_fmc: Added correct fifo to ILA. Updated interrupts
2014-10-31 14:49:29 +02:00
6fac294b6f
fmcomms2: Updated zc706 project to new interrupt system
2014-10-31 14:15:29 +02:00
91ea11041d
prcfg_mitx045: Upgrade of the project script.
...
- the design using the common PN monitor
- the first implemented logic will be the qpsk, to get a better result
- cosmetic changes
2014-10-31 12:18:00 +02:00
e450e78f13
prcfg: Update design to Vivado 2014.2
2014-10-31 12:05:19 +02:00
860a7caa56
prcfg: dac and adc to dma interface width is 64
2014-10-31 12:04:34 +02:00
ea194755e1
prcfg: Upgrade the QPSK logic
...
Regenerate the qpsk logic, with the new HDL coder, and modify the design to support the new files.
2014-10-31 11:59:29 +02:00
16cdae3001
mitx045_base: Delete unnecessary timing constraints.
2014-10-31 11:50:49 +02:00
07673b673a
adv7511_mitx045: Interrupt update
2014-10-31 11:46:27 +02:00
67bec719f7
mitx045_base: Interrupt update
2014-10-31 11:45:33 +02:00
b9f800ff65
fmcadc3: zc706: Fix connection to the system clock
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-10-31 11:06:16 +01:00
21f99b1c97
daq2: remove ila for kcu105
2014-10-30 15:26:29 -04:00
56859ad4c9
sys_dmafifo: use internal memory
2014-10-30 15:26:28 -04:00
5bd00df33a
adv7511_zc706: Interrupt update
2014-10-30 19:02:16 +02:00
d81484a6f3
adv7511_zed: Interrupt update
2014-10-30 19:01:17 +02:00
7ae003cf82
zed_base: Interrupt update
2014-10-30 19:00:05 +02:00
e0b7ef2f4f
scripts: Update scripts for PR design flow
...
+ Rewrite the pr_verify process, to improve verification time
+ Update the implementation flow: always the biggest logic will be implemented first, to achieve a better result
therefore force the tool to optimize the first logic with 'ExploreSequentialArea'
+ Make utilization report just from the PR pblock, that's more relevant as the utilization report of the whole fabric
2014-10-30 18:51:13 +02:00
02b32abefe
adv7511_zc702: Interrupt update
2014-10-30 18:42:14 +02:00
ba53e156e3
ZC702_base: Interrupt update
2014-10-30 18:39:49 +02:00
f595b86576
kcu105: lutram constraints for ies
2014-10-30 11:20:27 -04:00
d0a70380bf
kcu105: lutram constraints for ies
2014-10-30 11:19:55 -04:00
4c0e4d280f
dmafifo: internal version- light duty
2014-10-30 11:12:13 -04:00
360e7104b6
dmafifo: axi version- heavy duty
2014-10-30 11:12:12 -04:00
cfa1a93441
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-30 08:42:09 +01:00
56374cf592
usdrx1: Added synchronization, updated constraints, added timing check for a5gt project
2014-10-29 19:29:42 +02:00
cc265b6b9c
daq2/daq3/ad9625_fmc: Connect ADC DMA xfer_req signal
...
For proper operation the xfer_req signal needs to be connected from the ADC DMA to the DDR FIFO.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-29 18:15:54 +01:00
8c789104a6
ad9671: Fixed constraints. Modified system_timing.tcl so that it will fail if timing are not met
2014-10-29 18:25:56 +02:00
2e01ad2eec
ad9625_fmc/zc706: ps7 interrupt updates
2014-10-29 12:13:44 -04:00
b7946febfa
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-29 08:50:51 +01:00
f83622a2e6
daq2/kcu105: interrupt updates
2014-10-28 15:51:42 -04:00
4788d09620
vc707: interrupt updates
2014-10-28 15:42:55 -04:00
c9691fac64
ad9625_fmc: merge zc706 and vc707
2014-10-28 10:12:19 -04:00
627da6161b
ad9625_fmc: remove dma clock for now - zynq/non-zynq merge
2014-10-28 10:12:18 -04:00
36c7034bd6
ad7175: Fix dma issues
2014-10-28 16:00:06 +02:00
9e1d1c1b49
ad7175: Updated the AD7175 IP and project
2014-10-28 14:28:38 +02:00
fd66affa42
scripts: add default memory interconnect
2014-10-27 15:53:20 -04:00
fc4e002150
scripts: add mb cpu side
2014-10-27 15:53:19 -04:00
4f15f5c34c
adv7511: Update interrupts.
...
The ad_interrupts.v was used to concatenate the interrupts.
2014-10-27 19:48:05 +02:00
a870603db5
common_bd: Update the common block designs to the new IRQ path
...
Avoid the use of xil_concat module by using the ad_interrupts.
2014-10-27 19:44:25 +02:00
d04a545a41
fmcomms2: updated zc706 project with new constraint style
2014-10-27 19:27:36 +02:00
61c769e035
kc705: daq2 updates
2014-10-27 09:59:57 -04:00
d1e3993bd0
kcu105: daq2 updates
2014-10-27 09:59:56 -04:00
d471b61f3e
fifo: merge zynq and non-zynq
2014-10-27 09:59:54 -04:00
8b4d70eac6
daq2: merge zc706 and kcu105
2014-10-27 09:59:53 -04:00
54f341fad8
scripts: sdk export before timing check
2014-10-27 09:59:52 -04:00
4494998940
scripts: ignore another variant of reset warning
2014-10-27 09:59:51 -04:00
10b898a62d
zed_base: Fix IRQ layout.
...
Just a temporally fix of IRQ layout.
2014-10-27 14:46:26 +02:00
3645139e59
fmcomms6: Avoiding redefinition of system clocks.
2014-10-23 12:55:56 +03:00
dd5d57843d
fmcomms6: Update version of the ILA core
2014-10-23 12:30:55 +03:00
3dbfa8cda6
ad9434_fmc: Fix PN monitor and device interrupt
2014-10-23 11:29:14 +03:00
24e11b30b9
ad7175_zed: added the ad7175 ZED project
2014-10-23 06:15:17 +03:00
20d59ce39b
daq2: dma fifo modifications
2014-10-22 16:39:28 -04:00
4eeb50114f
daq2: rebase conflicts
2014-10-22 16:39:17 -04:00
43cdafe1e2
kcu105: iic-rstn removed
2014-10-22 16:33:52 -04:00
43fe20d141
Merge branch 'dev' of https://github.com/analogdevicesinc/hdl into dev
2014-10-22 17:19:37 +02:00
dcdba475f7
vc707_common: Fix net name sys_100m_resetn
2014-10-22 15:41:36 +03:00
a0d27a117c
usdrx1: Updated project with new synchronization mechanism. Fixed timing constraints
2014-10-22 13:20:44 +03:00
cd9033296c
ad9671_fmc: Fixed constraint files
2014-10-22 13:14:59 +03:00
17675863e0
all_projects: Fix the interrupt connections to preserve IRQ layout
2014-10-22 11:48:08 +03:00
767179dce9
adv7511_zc706: Fix IRQ layout
...
Fix IRQ connection, this layout works on Linux
2014-10-21 17:44:28 +03:00
2beaeb9176
projects/daq2/kcu105/system_constr.xdc: temp constrains
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-21 15:03:55 +02:00
8a4ab4e05a
projects/ad9434_fmc/common/ad9434_bd.tcl: Fix freeze - Design doesn't use SYNC
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-21 15:03:55 +02:00
d4a21d9775
ad9625_fmc: constraints fix
2014-10-20 10:00:39 -04:00
b3c784f76a
ad9467_fmc: Made some cosmetic changes on the block design script.
2014-10-20 13:28:34 +03:00
4b8720b551
fmcomms2_zc706: Remove top level constraints
...
Remove all the unnecessary top level constraint definitions.
2014-10-20 13:25:01 +03:00
7115864b4c
ad9434_fmc: Remove top level constraints
...
Remove all the unnecessary top level constraint definitions.
2014-10-20 13:23:37 +03:00
5deffd57b1
zed: Remove top level constraints
...
Remove top level constraints from the ZED base design.
2014-10-20 13:20:27 +03:00
0c56e5b912
ad9434_fmc: Fix GPIO width
...
GPIO port width is 15 instead of 32
2014-10-20 10:59:30 +03:00
7f8270d74b
ad9625_fmc: generic dma fifo for zynq and non-zynq boards
2014-10-17 14:38:16 -04:00
0b30f98640
ad9625_fmc/zc706: remove top level constraints
2014-10-17 14:38:15 -04:00
f3c9627cae
adi_project: demote reset warnings to info
2014-10-17 14:38:13 -04:00
14ccdaaa78
kcu105: removed spdif reset
2014-10-17 14:00:00 -04:00
380eeec013
daq2/kcu105: ethernet fix
2014-10-17 13:48:35 -04:00
fca0714478
adv7511/kcu105: ethernet fix
2014-10-17 13:48:33 -04:00
e73b3b52dc
kcu105: ethernet fix
2014-10-17 13:47:50 -04:00
2600b1f359
daq3: tx interleave and dma fifo axi streaming
2014-10-15 14:51:04 -04:00
6d76e0b768
zc706: remove top level constraints
2014-10-15 14:51:02 -04:00
5715c5b28f
dmafifo: axi stream interface
2014-10-15 14:50:57 -04:00
0aed11fa6c
adi_project: demote useless warnings
2014-10-15 14:50:54 -04:00
4d4a7981f2
fmcomms1: Connect DMA controller directly to the HP ports
...
The AXI DMAC controller nativly supports AXI3, there is no need to insert a interconnect to do protocol conversion.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:46:07 +03:00
7d3be14ab5
common: Connect audio clkgen reset
...
While we are at it also hide the unused locked pin.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:44:46 +03:00
fd89458708
common: Set cpu interconnect strategy to minimize area
...
There will rarely be concurrent access to the peripheral control bus
interconnect, so there is no need to optimize for performace. Setting the
interconnect strategy to minimize area can reduce the resource usage by
~90%.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-15 18:43:54 +03:00
d2a04856a9
common: Fix xlconstant output pin name
...
On 2014.2 xlconstant output pin name is 'dout'.
2014-10-15 15:37:06 +03:00
02802644bf
fmcjesdadc1: Fix a few warning and issue with ILA
...
+ GPIO width is 15
+ Fix ILA core
2014-10-15 15:37:05 +03:00
865cbab3a2
ad9671_fmc: Updated a5gt project with start of frame information
2014-10-15 10:53:33 +03:00
8934a66013
usdrx1: Update project so that the AD9671 cores can be synchronized
2014-10-13 17:06:40 +03:00
f528873fa9
fmcomms2: Add an additional SPI interface for up/down converter board
...
Supported carriers are: ZC706, ZC702 and Zed.
2014-10-10 18:47:07 +03:00
ca4c961891
fmcomms2: Use ad_iobuf instance on system_top
...
Use ad_iobuf instance on system top, instead of separate IOBUF instances.
2014-10-10 18:45:39 +03:00
e21d26e456
fmcomms2: Cosmetic changes
...
Get rid of unwanted whitespaces.
2014-10-10 18:25:17 +03:00
fe8a076b2e
fmcomms2: Cosmetic changes on *_bd.tcl script
2014-10-10 17:06:32 +03:00
7a9e694446
fmcomms2: Connect DMA directly to the HP ports
...
The DMA controller is able to send AXI3 compatible requests, no need to add
a interconnect for protocol conversion in between the DMA controller and the
HP port.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:14 +03:00
87047fd83e
fmcomms2: Set dac_unpack channels to 4
...
There are only 4 DAC channels in the fmcomms2 design, so set the number of
channels of the dac_unpack core to 4. This slightly reduces resource usage
as well as reducing the DMA alignment requirement from 128bit to 64bit. The
later value is what existing applications expect the alignement requirement
to be.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-10-10 16:25:06 +03:00
43e9b0c7a6
common: Disable TTC0 MMIO routing for PS7
...
We do not use the ttc0 to MMIO routing, but it is enabled by default, so
explicitly disable it.
2014-10-10 16:19:51 +03:00
e361bbbd04
Revert "fmcomms2_udc: Initial check in"
...
This reverts commit ddc7c845e9
2014-10-10 14:48:55 +03:00
7659f3438c
AD9467: Fixup swapped net names
...
Signed-off-by: Paul Cercueil <paul.cercueil@analog.com>
2014-10-10 12:33:07 +03:00
adf4893a27
usdrx1: remove constraints and other changes
2014-10-09 15:25:08 -04:00
ddc7c845e9
fmcomms2_udc: Initial check in
...
FMCOMMS2 with an additional SPI port for the up/down converter board
2014-10-09 19:01:22 +03:00
6f77af4aff
fmcjesdadc1: Upgrade project to 2014.2
2014-10-09 18:55:27 +03:00
2da395926e
fmcomms2: Upgrade project to 2014.2
2014-10-09 18:54:33 +03:00
4f6aa159b8
mitx045: Base design now support 2014.2
2014-10-09 15:11:28 +03:00
edeeafa47d
ad9671_fmc: Added sof information to the AD9671 driver
2014-10-09 14:52:25 +03:00
072e11c661
ad9467_fmc: Upgrade the axi_quad_spi core
2014-10-08 15:22:58 +03:00
fc38249150
ad9467 ZED: Fix over range signal path, and the dma interface.
2014-10-08 11:24:44 +03:00
15db557bd6
ad9467 ZED: Cosmetic changes on bd script.
2014-10-08 11:24:32 +03:00
82717b354a
ad9467_fmc : Upgrade project to 2014.2
2014-10-08 11:21:43 +03:00
b2d0260130
ad9467_fmc: Prevent to use concatenation module on SPI interface
...
This module cause unnecessary issues during version upgrades.
2014-10-08 11:20:45 +03:00
27153fff41
ad9625x2_fmc: updated to 2014.2
2014-10-07 16:05:09 -04:00
2dfcb0c599
usdrx1: Initial commit for a5gt
...
axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
95842b8949
ad9434_fmc: Fix adc_valid signal path
2014-10-07 18:02:33 +03:00
115f33b8d6
ad9434_fmc: Fix pin constraints for ZC706
2014-10-07 17:58:29 +03:00
c1213ffe71
ad9434_fmc: Fix SPI interface
2014-10-07 17:51:14 +03:00
cd42345324
projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-10-07 09:17:24 +02:00
bca8ec0160
daq2: 2014.2 and ver.d
2014-10-06 14:56:01 -04:00
c375b5b26e
daq3: vivado build
2014-10-06 10:34:02 -04:00
525373fc04
daq3: daq2 copy
2014-10-06 10:34:00 -04:00
210da4116f
scripts: initial commit
2014-10-03 16:13:34 -04:00
f0927afd0b
ad9625_fmc: add dma fifo for non-zynq
2014-10-01 14:51:14 -04:00
89964be59e
fmcomms1: Updated project to vivado 2014.2
2014-09-30 10:32:18 +03:00
041d8faaf7
common: Updated common projects for ac701/kc702/zc702/zed to vivado 2014.2
2014-09-30 10:31:00 +03:00
922bc6f03a
fmcadc3: 16bit - but ignored 4 lsb(s)
2014-09-29 15:26:30 -04:00
3c25c1171d
fmcomms1: Fixed missing sample issue on ZC706. Added modifications for all other platforms
2014-09-26 10:28:07 -04:00
87c4c73e22
ad9434: Fix adc_clk constraint
...
ADC clock is 500 Mhz.
2014-09-25 16:54:06 +03:00
82ed885b53
ad9434: Fix SPI line physical constraints
...
SPI lines are not differential.
2014-09-25 16:53:16 +03:00
ccb0b135ca
ad9434: Fix the adc to dma interface.
...
All the device2dma interfaces needs to have a generic form : (data, enable, valid)/channel
2014-09-25 16:50:09 +03:00
683561b67d
AD9434: Initial check in of the library and project with ZC706
2014-09-24 18:27:17 +03:00
1d4bc47cea
ad9265: Initial commit
2014-09-23 22:51:42 -04:00
296983707b
usdrx1: Updated project to 2014.2
2014-09-23 22:45:50 -04:00
5af2474d51
usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization
2014-09-23 22:44:33 -04:00
bdf01738a1
ultrasound: disconnected ADN4670 chips from SPI lines.
...
Connected everything to ground so that the the clock selected is 0 and all outputs are enabled
2014-09-23 22:30:42 -04:00
7e40f99fe9
fmcomms2: Improved constraints for ac701 and zc702. Fixed common design so that ILA works correctly on microblaze based systems
2014-09-23 22:28:27 -04:00
577441bd0c
daq1: clean up dma interfaces
2014-09-23 14:23:41 -04:00
7c98a783c5
2014.2 updates
2014-09-23 12:32:33 -04:00
1682d9da10
fmcadc3: initial updates
2014-09-22 11:27:17 -04:00
5e3076d770
fmcadc3: daq2 copy
2014-09-22 11:27:16 -04:00
dd7bac41c1
daq1 : Update project to 2014.2
...
- Cores are upadted
- Concat module does not swap output anymore
- Clock signal name ps7_clk_* changed to clk_fpga_*
2014-09-22 17:33:50 +03:00
f2cd7626f5
adi_project : ZC706 board name changed on 2014.2
2014-09-22 17:33:49 +03:00
fb5d212370
daq2/kcu105: fixed timing violations
2014-09-19 15:55:42 -04:00
751bdd6cfc
daq1: Update the constraint file
...
- tx_ref_clk and rx_sysref need to be differential
- cosmetic changes
2014-09-19 18:22:57 +03:00
f43b5d707e
fmcomms2: Reduced clock frequency for ILA to meet timing for ZED
...
Modified ZED constraints to 250 MHz for the clock from AD9361
2014-09-16 16:08:28 -04:00
d33fb07587
usdrx1: Modified the GPIO assignments so that board specific GPIOs start from GPIO 32.
...
GPIOs for which the directions is known, have been specifically assigned.
The SPI clock has been changed to a lower frequency.
2014-09-16 15:56:19 -04:00
d4db53c3b0
usdrx1_spi: Modified module to be compatible with altera
2014-09-16 15:53:11 -04:00
a3dbd5ac00
projects/common/vc707/vc707_system_bd: AD9625_FMC update to 2014.2
...
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
2014-09-16 14:59:36 +02:00
a91f4bb6b9
daq1: General updates
...
- Add additional GT setups
- Use channel PLL instead of quad PLL
- Add additional ILA probes for debug
2014-09-13 00:23:11 +03:00
d8651cdd2e
fmcomms2: c5soc: Set dac_util_unpack number of channels to 4
...
We only do have 4 channels in this design. Reducing the number of supported
channels for the dac_util_unpack core to 4 from 8 lowers the DMA alignment
requirement from 128bit to 64bit. We need this since applications only
expect a DMA alignment requirement of 64bit.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:15:12 +02:00
ecc498313c
fmcomms2: c5soc: Connect ADC, DAC and VGA DMA to different bridge interconnects
...
We have enough bridge interconnect to give each DMA its own, so use them.
This makes sure that they do not interfere with each others transfers to
much. The SDRAM controller side of the FPGA2SDRAM bridges FIFO runs at a
much faster frequency then what we are able to use in the fabric. So its
better to do the arbitration on that side of the bus to make sure that we
can utilize the buses in the FPGA fabric to the maximum for each DMA core.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-12 16:14:07 +02:00
61f21a17b3
fmcomms2:c5soc project upgraded with util_dac_unpack
2014-09-11 15:13:09 -04:00
4c1c50788e
fmcomms5: c5soc: Fix typo
...
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 17:15:10 +02:00
41cc92ef49
Remove BASEADDR/HIGHADDR parameters
...
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
647a26e19c
projects/common/vc707/vc707_system_bd.tcl: Select Linux MMU settings
2014-09-10 17:40:36 +02:00
c7989925c5
fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock
...
Otherwise we get timing errors for the reset signal that is generated in the
50MHz clock domain, but used in the VGA PLL clock domain.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
328205c31d
fmcomms2: c5soc: Set DMA transfer length to 24 bits
...
14 bits is a bit to low and we use 24 bits everywhere else as well.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-09 15:05:06 +02:00
50faf0c53a
Remove executable flags from non-exectuable files
2014-09-09 15:05:06 +02:00
b58e425b44
daq2/kcu105: timing improvement -register slices hang
2014-09-08 10:24:56 -04:00
6e389b8c47
motor_control: Updated the FOC IP and the encoder connections to the IP
2014-09-06 15:58:03 +03:00
669462e0f6
ad9625x2: updates on pcores
2014-09-05 12:25:43 -04:00
72f31370ef
a5gt: ethernet-fpga lvds mode
2014-09-04 11:19:25 -04:00
3deb55bb98
a5gt: ethernet i/o changed to lvds
2014-09-04 11:19:24 -04:00
dfb94f7b68
motor_control: Modified foc_controller to be compatible with other cores
2014-09-03 12:09:37 +03:00
9f3461b130
fmcjesdadc1: Added support for KC705
2014-09-02 18:02:25 +03:00
17122661d2
fmcomms2_pr: Fix file path on ZC706/system_bd.tcl
2014-09-01 18:49:55 +03:00
2ce7695bf7
fmcjesdadc1: Initial commit of VC707 version
2014-09-01 18:47:01 +03:00
9a80fec4e4
fmcjesdadc1: Delete trailing whitespaces
2014-09-01 18:45:20 +03:00
d08d0cd70b
motor_control: added the MW FOC IP and updated the design
2014-09-01 18:35:21 +03:00
ee752ec08a
daq1: Initial commit
2014-09-01 18:34:31 +03:00
a773cc4992
usdrx1: updated project
...
ad_jesd_align wasa updated to be able to work with frames that have more than 4 octets per frame
2014-09-01 15:18:39 +03:00
95c143412d
fmcomms2: Modified design to work with 4 channel util_adc_pack
2014-08-29 13:53:59 +03:00
da913864c9
ad9671_fmc: updates to match recent core changes
2014-08-28 13:16:52 -04:00
5a42c10233
projects/fmcomms2/c5soc: Added video output. HPS SPI was replaced by 3 Wire SPI.
2014-08-27 21:46:23 +03:00
c435edf194
ad9652/zc706: fix dma write
2014-08-27 10:44:39 -04:00
7b280b3bbf
fmcomms6: zc706 build-only version
2014-08-27 10:44:37 -04:00
0e909647b4
fmcomms6: initial checkin
2014-08-27 10:44:36 -04:00
a49eb5853b
ZED, ZC702: Added contraints so that projects can successfully synthesize on linux systems
...
For ZC706 Fixed one constraint which was not correct
2014-08-26 16:28:41 +03:00
5f21f54463
fmcjesdadc1: zc706 version
2014-08-25 14:28:57 -04:00
cb29b83b05
a5gt: updates to match a5gt
2014-08-25 10:46:59 -04:00
76ffb939e5
zc706: ad9625 copy
2014-08-22 11:24:24 -04:00
fe1eaefcff
fmcomms1: zc706
2014-08-22 09:08:55 -04:00
280260e54c
c5soc: dmac separated slave and master id widths
2014-08-22 09:08:54 -04:00
f3f8414d81
kcu105: changes for ad_iobuf
2014-08-15 15:01:52 -04:00
b481df0b5f
library: local constraints async groups
2014-08-14 15:09:51 -04:00
39bb7ca231
a5soc: fmcjesdadc1+hdmi version
2014-08-14 09:05:38 -04:00
a54e4edb08
Add xfest14 PMODs project
...
This project has a SPI controller connected to each of the ZED boards PMOD
ports JA, JB, JC, JD pin 1-4. Pin 7-10 are connected to the PS7 general purpose
GPIOs, except for JC where it is connected to the PS7 UART controller.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-08-12 10:14:16 +02:00
96969079ce
a5soc: fixes for 14.0 and spi conflicts
2014-08-11 16:46:37 -04:00
902d5b0da2
prcfg: Update fmcomms2_pr for ZC706
2014-08-05 17:55:31 +03:00
9dfbf4a9a6
prcfg: Update the prcfg logic to the new ad9361 interface
2014-08-05 17:54:37 +03:00
e9f8c0fb5f
fmcomms5: ZC706 modified constraints for linux build machines
2014-08-01 18:09:55 +03:00
6c6cab0e16
fmcomms2: ZC706 modified constraints for linux build machines
...
The added constraints allow the project to successfully pass timing on some ubuntu or debian build machines.
2014-08-01 17:34:36 +03:00
663588eeaf
daq2/kcu105: working ddr version
2014-07-29 09:15:30 -04:00
9cdd4107cd
fmcomms5: ZC702: add reset_b and fixed system_top
2014-07-25 15:24:11 +03:00
7bee85423d
c5soc: removed stp/cdf files
2014-07-24 20:53:08 -04:00
59759a8ab3
c5soc: working hdl version
2014-07-24 20:51:41 -04:00
7000897031
fmcomms2, fmcomms5: updated util_adc_pack and util_dac_unpack
...
The cores now support up to 8 channels, in 1, 2, 4, 8 channel active configuration
2014-07-24 19:57:22 +03:00
a68f634de9
fmcomms5: Added resetb for the second AD9361
2014-07-24 17:31:30 +03:00
49a77c0413
prcfg: Generate configuration files to *.bin
2014-07-24 09:43:00 +03:00
db2386a351
daq2/kcu105: latest mig updates
2014-07-23 16:25:55 -04:00
db1c931736
ad9625_plddr: PL DDR3 fixes
...
- Modified the axi slave interface handler
- Increased the rfifo_mem input depth to prevent overflow
2014-07-23 19:34:44 +03:00
4da8100fe5
ad9625_plddr: Delete trailing whitespaces.
2014-07-23 19:31:07 +03:00
c0e31aa6c2
daq2: latest hardware
2014-07-21 09:06:57 -04:00
e3320c43cb
fmcomms2/c5soc: programmer file
2014-07-21 09:06:55 -04:00
9b9e0c6a56
fmcomms2/c5soc: signal tap
2014-07-21 09:06:54 -04:00
65879d621f
daq2: updates for the new hardware
2014-07-21 09:06:53 -04:00
2b6ce1e504
zc706_plddr3 : Fix axi_fifo2s_axi_mrst net
2014-07-21 15:10:36 +03:00
2955b9db78
fifo2s: flush if no request, c5soc: 14.0
2014-07-15 16:25:33 -04:00
e7d5d79e42
daq2/kcu105: gth up and running - as it is commit
2014-07-10 10:56:37 -04:00
085512a738
fmcomms2_pr: Fix the source path for prcfg_setup
2014-07-10 17:54:41 +03:00
95701fbd0e
fmcomms2_pr : PR initial check in
2014-07-10 10:41:48 +03:00
b434fe6dd5
fmcomms5: register map changes
2014-07-08 16:57:43 -04:00
39ac29bb01
AD9361: Altera, modified address width so that all registers are accessible
...
Modified qsys project with the new address span
2014-07-08 10:41:51 +03:00
10c21a343a
fmcomms2/c5soc: Fixed the spim0_ss_in_n value.
2014-07-08 10:07:31 +03:00
c53b257ab1
fmcomms2/c5soc: Fixed the MOSI and MISO pin assignments.
2014-07-07 22:28:25 +03:00
c75e6b3043
kcu105 pwr-good removed
2014-07-07 09:56:13 -04:00
f2bf5ced04
ad9625: register map updates
2014-07-03 14:30:03 -04:00
f94cbbb0aa
daq2: register map updates
2014-07-03 12:36:37 -04:00
a388ccab0a
fmcomms2/c5soc: initial checkin
2014-07-02 14:56:00 -04:00
9a08189b93
c5soc: initial a5soc copy
2014-07-01 13:09:38 -04:00
c1b7fc17f5
c5soc: initial a5soc copy
2014-07-01 13:05:26 -04:00
60dd14bcdb
a5soc: removed jtag master control
2014-07-01 12:27:37 -04:00
ba7955c531
fmcomms2: register map modifications
2014-06-26 10:09:03 -04:00
92e525d573
ad9250: register map updates
2014-06-25 15:24:48 -04:00
e38813fa9f
fifo- monitor status signals
2014-06-25 12:15:13 -04:00
57bb3705f2
zc706-plddr3: read changes to lower dma clock
2014-06-25 09:20:58 -04:00
3d8d576532
prcfg_script: Update the PR flow script
...
+ Make part global
+ No need the Explore directive on implementation
+ Fix some reference to pr module
+ Fix the pr_verify function
2014-06-13 20:33:59 +03:00
7efd6149f8
daq2: initial checkin
2014-06-12 15:54:25 -04:00
b1b9067512
ad9625x2_fmc: added multi-sync support
2014-06-12 15:45:35 -04:00
6ea7dd7fc3
kcu105: pwr-good added
2014-06-12 15:22:31 -04:00
6e444559b5
usdrx1: global clock fix
2014-06-10 18:09:49 +03:00
2d27f88588
ad9625_fmc, ad9625x2_fmc: initial checkin
2014-06-09 16:40:48 -04:00
bef6a9c32c
axi_ad9361: Split dma data into individual channels for both ADC and DAC
2014-06-07 17:15:31 +03:00
2837d788a6
mitx045: Added I2S core to the base design
2014-06-06 17:53:47 +03:00
bd8d355b05
scripts: Update adi_prcfg_project.tcl
...
Define a new parameter for the prcfg_init_workspace process:
prcfg_name_list.
2014-06-06 15:00:23 +03:00
cf56a568c6
kcu105: GTH updates
2014-06-05 14:27:38 -04:00
f452e40192
scripts: Initial check in of non-project flow
...
These processes are used for projects with partial
reconfiguration. The used design flow in these cases is the
non-project (batch) design flow.
2014-06-05 14:33:27 +03:00
45325b7c0d
mitx045: minor changes in common and ADV7511 projects
2014-06-03 19:24:12 +03:00
f695a45394
global clock fix
2014-06-03 09:23:23 -04:00
f217139770
fmcomms2: added project for mini_itx, xc7z045 version
2014-06-02 14:06:10 +03:00
c52327d0c6
common,adv7511: Added mitx045 platform.
2014-06-02 11:08:03 +03:00
877b81a373
ad9625/vc707: working version
2014-05-30 15:07:23 -04:00
c789dce77e
ad9625/zc706: added pl ddr3 fifo changes
2014-05-29 12:59:29 -04:00
56ddce1e8c
dmac: create fifo interface to avoid being treated as axi control stream
2014-05-27 10:25:14 -04:00
1d53d79e25
fmcomms2/common: Fix ad9361's interface
...
Loopback the l_clk to clk. l_clk is the device sampling clock, clk is used to
synchronize the cores in case of a multiple device configuration.
2014-05-21 10:09:54 +03:00
25e4520726
fmcomms2/common: Delet trailing white spaces
2014-05-21 09:47:37 +03:00
bab90a19c2
fmcomms5/zc702: removed unused ila cores
2014-05-20 14:42:48 -04:00
7e6b4ea9d0
fmcomms5: ignore only common clock to external clocks
2014-05-19 20:38:41 -04:00
9a36075324
moved fmcomms5
2014-05-19 13:49:49 -04:00
f73819f4d4
zc706: pl ddr3 initial checkin
2014-05-13 16:19:53 -04:00
f3f8374c75
ad9671: 2lane version
2014-05-08 18:33:26 -04:00
c5b3dd3643
vc707 base : tcl update
...
- Added missing address space
- Connect the sys_audio_clkgen/reset
2014-05-08 12:30:25 +03:00
3ac1da178e
kcu105: sane except for ddr4/ethernet
2014-05-06 15:39:05 -04:00
51c0ee1e20
ml605: tcl updates
2014-05-06 09:29:21 -04:00
e7cbaca216
ml605: initial checkin
2014-05-05 11:24:12 -04:00
53af7f3c1f
ml605: initial checkin
2014-05-05 11:20:26 -04:00
4d4f66fbdd
a5soc: increase pipeline for qsys
2014-05-04 10:38:53 -04:00
b55d0d7ad1
a5soc: constraints for false paths
2014-04-30 16:14:30 -04:00
a10043c4f4
kcu105: base complete with ethernet errors
2014-04-30 14:41:43 -04:00
ef60cce15e
kcu105: added
2014-04-30 14:41:40 -04:00
be69c0c330
kcu105: initial checkin
2014-04-30 14:41:39 -04:00
9900a56fa5
kcu105: initial checkin
2014-04-30 14:41:37 -04:00
0b1ce14842
a5soc: basic hardware build
2014-04-30 12:40:27 -04:00
99d66e7580
a5soc: initial-copy version
2014-04-30 12:40:26 -04:00
681e4239df
ad9671/a5gt: subclass-0 version
2014-04-28 21:31:21 -04:00
06873aeddb
ad9671/a5gt: subclass-0 version
2014-04-28 21:31:20 -04:00
d66f256f1c
9671/a5gt: 9671-sc1 version
2014-04-28 21:31:19 -04:00
f55288ef5d
ad9671: altera - base changes
2014-04-28 21:31:18 -04:00
2e7bf190b5
initial checkin-9250 copy
2014-04-28 21:31:15 -04:00
01de117b5f
motor_control: Changed controller to PID controller. Some estetic changes
2014-04-28 17:57:51 +03:00
dfc2bba335
ad9671: updates to allow default adc setup routines
2014-04-23 16:39:28 -04:00
a1bcf345c6
ad9671: fix spi connections
2014-04-21 13:46:44 -04:00
213e852e11
motor_control: Initial commit
2014-04-18 18:57:18 +03:00
ba44ee63be
fmcomms1: modified the fmcomms1_bd.tcl to make it compatible with latest wfifo
2014-04-14 17:04:04 +03:00
179d6d601c
adi_board.tcl : Use 'global' instead of '$::'
2014-04-14 11:45:35 +03:00
38126c404c
usdrx1: spi signal definitions
2014-04-11 14:28:23 -04:00
06b28d2e24
ad9671: compile fixes
2014-04-11 14:28:22 -04:00
e92e6b2fd5
ad9671_fmc: changed for ad9671-fmc
2014-04-11 14:28:21 -04:00
72e318a247
ad9671_fmc: initial checkin
2014-04-11 14:28:20 -04:00
99ef34936f
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-11 18:14:08 +03:00
d0f04fd788
fmcomms1: Commit AC701 and VC707 projects
2014-04-11 17:35:25 +03:00
c718169f27
adi_board.tcl : Fix the address assignment command
...
A lot of cores have more than one address segments, therefor need
to filter out the segment of the axi lite interface
2014-04-11 16:14:56 +03:00
cf5b9b51fd
adi_board.tcl : Fix spi ports and hp clocks
2014-04-11 15:31:12 +03:00
37e2059fd0
adi_board.tcl : General update
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- Split the adi_dma_interconnect to two procedure:
adi_dma_interconnect and adi_hp_assign
- Fix the adi_spi_core
- Fix the adi_interconnect_lite
2014-04-10 18:29:14 +03:00
96541f0a7f
usdrx1: zc706 updated for usdrx1
2014-04-10 11:05:13 -04:00
6f36f74eea
usdrx1: common board files
2014-04-10 11:05:11 -04:00
ac1c145a61
usdrx1: initial checkin
2014-04-10 11:05:10 -04:00
dc7b3e085c
axi_dmac: Fix issues with non 64-bit AXI masters
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Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:54:22 +02:00
9d19145713
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-04-10 10:50:53 +03:00
5aac9d7288
FMCOMMS2 added sync option
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Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
fbfd658f0d
zc706: added pl ddr3 mig
2014-04-09 15:58:12 -04:00
e73952a694
ad9467 : initial checkin
2014-04-09 17:34:40 +03:00
5b0e37b97a
adi_project.tcl : Modify implementation strategy
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- Change implementation strategy to Performance Explore.
At some projects, this could prevent timing issues, it not
increase the overall implementation time in a dramatic way.
2014-04-07 15:02:38 +03:00
33979fc533
fixes to improve timing - fifo for clock domain transfers
2014-04-04 13:49:53 -04:00
6a19b34a00
a5gt: added tightly coupled memory
2014-04-03 20:50:17 -04:00
04ab34c8ed
a5gt: ethernet assignments
2014-04-03 20:50:16 -04:00
12e5cc91bd
make signaltap/timing part of the flow
2014-04-03 20:50:15 -04:00
d0a8b4a63c
kc705,common: Mem_interconnect maximize performance
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For FMCOMMS1, when both the ADC and DAC DMAs are active, the system was
unstable. With this fix, it the system seems to be stable.
2014-04-03 15:59:33 +03:00
e85153b5dd
altera hal version
2014-04-01 21:12:11 -04:00
04df908fbf
altera-fmcjesdadc1 initial checkin
2014-04-01 12:01:57 -04:00
0d678b89ed
altera a5gt fmcjesdadc1 setup
2014-04-01 11:46:37 -04:00
8deb36ce08
adi_board.tcl: All procedures works on Zynq/Microblaze
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General patch for the integration procedures. Tested on kc705 and
zed.
2014-04-01 16:19:24 +03:00
9676146725
FMCOMMS2 AC701 Project
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Not tested - must program Vadj on board
2014-04-01 15:35:44 +03:00
e597467447
FMCOMMS2 VC707 Project
2014-04-01 15:34:29 +03:00
814b0d72d6
Modified Reset signals for FMCOMMS2 base design
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Made all resets the same (sys_100m_resetn)
2014-04-01 15:32:48 +03:00
fbafaa8507
MicroBlaze base system: Fix a few net names
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Every interconnect interface net name follows the convention:
<interconnect name>_<interface name>
No changes in logic or any connection!
2014-04-01 10:40:35 +03:00
f0b8b8f6c0
FMCOMMS1: KC705 updated system_top and constraints
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Needed to be compatible with the latest common file
2014-03-31 17:49:10 +03:00
14b82c03dd
FMCOMMS1: Several modifications in the base design
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Corrected the ADC/DAC interrupt location for microblaze systems
Removed the ILA clock generation from sys_audio_clkgen and created a
separate clock generator
All system is reset from the same source
2014-03-31 17:44:57 +03:00
a881557645
base_design: Fixed AC701 and VC707 contstraints
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AC701: Modified the IOSTANDARD for some of the pins to correspond to the
AC701 user guide.
VC707: Fixed naming for some system clocks
2014-03-31 17:38:20 +03:00
4ef88a3bed
adi_board.tcl : Patch for adi_spi_core process
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- Fix indentation
- Pacth for adi_spi_core process
2014-03-31 16:41:07 +03:00
7f4f200fce
Project scripts: Initial check in of adi_board.tcl
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The script contains integration tcl processes.
2014-03-26 19:08:56 +02:00
f9a67371c0
Zynq Base System: Reset is synchronized to lowest system clock
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System reset (sys_100m_reset) is synchronized to lowest system
clock (FCLK0), via a Processor System Reset module
2014-03-26 17:58:14 +02:00
ad5ef35b48
fmcomms1: modified *_bd.tcl files formatting
2014-03-26 12:05:42 +02:00
8f7d4c9b26
FMCOMMS1: Fixed typo in common/fmcomms1_bd.tcl
2014-03-25 14:34:55 +02:00
0f10623be4
AC701/VC707: Define common variables
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Define variables sys_zynq, sys_mem_size, sys_addr_cntrl_space.
2014-03-25 14:24:51 +02:00
2070c66b87
Fmcomms1: Initial commit for KC705
...
Modified common project so it can be compatible for both ARM and
Microblaze based systems.
2014-03-24 16:52:24 +02:00
aa7b0bb4dd
VC707 basesys: General fixes, actual status: working
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- Add an auxiliary cpu interconnect
- Add an auxiliary interrupt concatenation module
- Add new MIG file, current frequency of the DDR interface is 100
Mhz
- Memory interconnect optimisation strategy is 'Maximize
Performance'
2014-03-24 13:07:48 +02:00
b94acf78aa
AC701 bases sys: Add an auxiliary cpu interconnect
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- Add an auxiliary cpu interconnect, the KC705 base system was
used as reference
- Base system is tested and working
2014-03-24 13:01:52 +02:00
792e8a208d
KC705 base system: Make a few cosmetic changes
2014-03-24 12:55:37 +02:00
f8c1179bc1
FMCOMMS2 KC705 Project.
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Added the files required for the FMCOMMS2 KC705 project.
Both DMA and DDS work.
2014-03-24 11:48:52 +02:00
8a08031dce
AC701: Modify interrupt concatenation
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- Interrupt concatenation is the same as in case of KC705
2014-03-24 10:20:56 +02:00
13b4dd07d0
KC705 base system: Modify interrupt concatanation
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- Add an aditional interrupt input net for the sys_concat_aux_intc
module
2014-03-21 14:45:18 +02:00
c6143dbfaf
KC705 base system: Delete trailing whitespaces.
2014-03-21 14:42:27 +02:00
31a1ff384d
FMCOMMS2 Base Design tcl modified
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Added support for both Zynq and MicroBlaze projects
2014-03-21 09:57:52 +02:00
3a0d1282b7
Fix the remaining issues
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- Swap the IO locations of ports vsync and hsync
- Change the mem_interconnect optimization strategy to Maximize
Performance
2014-03-20 14:36:01 +02:00
698e9f4757
Added phys_opt_design step for fixing timing
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The FMCOMMS1 meets timing on ZED/ZC702 only if the phys_opt_design step
is part of the implmentation flow, with the Explore argument.
"This step performs physical optimizations such as timing-driven
replicaiton of high fanouts nets to improve timing results"
2014-03-19 16:42:44 +02:00
7cdab9b5b0
Change the internal clock generator to Clock Wizard
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- Using a Clock Wizard Module, in place of the DDR Controler's MMCM for internal clock
generation.
2014-03-18 17:24:45 +02:00
9d65071235
Merge branch 'master' of https://github.com/analogdevicesinc/hdl
2014-03-18 15:30:29 +02:00
2c898bf3a2
Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project
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ZC706 runs rx_clk at 250 MHz.
ZC702 and ZED run rx_clk at 200 MHz due to slower fabric.
The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly.
Both DDS and DMA mode work.
2014-03-18 15:27:42 +02:00
f3c503cfb8
Merge branch 'master' of github.com:analogdevicesinc/hdl
2014-03-17 21:33:13 -04:00
dc44703cf1
zynq/non-zynq: identical signal names and instances
2014-03-17 17:02:03 -04:00
a6da4ca01c
zynq/non-zynq merge variables
2014-03-17 16:39:52 -04:00
ab8627e669
fmcomms1: Changed ILA data capture and sys constraints
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The ILA can not work at 250MHz on ZED/ZC702. Because of this, the data
path was modified from 28bits@250MHz to 56bits@125MHz, by using a FIFO.
The ZED/ZC702 max BUFG frequency is 464MHz, which corresponds to a 2.16
period so the constraints were modified accordingly.
2014-03-17 15:50:01 +02:00
ee56db8d50
FMCOMMS2: Modified FCLK2 to 125 MHz, and xdc file
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tcl: FCLK2 was modified from 100 MHz to 125 MHz.
xdc: rx_clk period constraint was redefined from 8ns (125 MHz) to 4ns (250 MHz)
2014-03-14 16:27:56 +02:00
7a6ce70e19
Fix default repository path for adi_project.tcl
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Projects can be build by running 'source system_project.tcl' in
Vivado Tcl console.
2014-03-13 10:28:16 +02:00
a6c3cb29c6
Modified SPI and ILA in fmcomms2_bd.tcl
2014-03-12 16:52:22 +02:00
92aaf0bd51
FMCOMMS1: Updated projects and axi_ad9643 core
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ZC702: Removed invalid address segments. Changed the constraints
for adc_clk to minimum possible value in order to meet timing.
ZED: Change the constraints for adc_clk to minimum possible value, in
order to meet timing
AXI_AD9643: Corrected the number of bits in the adc_mon_data bus
2014-03-12 16:23:41 +02:00
66c6b2b182
fmcomms2: added
2014-03-11 20:04:26 -04:00
f8ab734918
projects/fmcomms1: added
2014-03-11 12:16:25 -04:00
e1f23e7d49
Merge branch 'master' of github.com:analogdevicesinc/hdl
2014-03-11 09:58:34 -04:00
f3ae57a53e
global clock and reset names
2014-03-11 09:57:59 -04:00
75963ab376
Initial check in of VC707 base project
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- All source files for the VC707 base project
- Update the common base system to the new naming convention
2014-03-10 17:26:17 +02:00
793bf2f350
Change the adi_project_run process to prevent "const_type UCF" issue
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- Set the constraint type to XDC before run the synthesis
2014-03-07 11:06:11 +02:00
5c3b65d01b
adv7511: kc705/ac701 updates
2014-03-06 09:36:50 -05:00
b0a1fab743
adv7511/kc705: added
2014-03-05 10:43:16 -05:00
360f10395a
initial checkin
2014-03-03 13:42:25 -05:00
82115b138e
adv7511/ac701: initial checkin
2014-03-03 13:40:24 -05:00
c89477be5a
projects/adv7511: zynq boards
2014-03-03 10:16:49 -05:00
350ec5e633
changed path settings
2014-03-03 10:06:36 -05:00
3c0ea759a0
changed path settings
2014-03-03 10:06:02 -05:00
ddac1a8834
added common board files
2014-02-28 21:17:01 -05:00
Adrian Costina
Istvan Csomortani
Lars-Peter Clausen
Rejeesh Kutty
Nicholas Pillitteri
dbogdan
Michael Hennerich
Paul Cercueil
acozma
ATofan
Istvan Csomortani