Commit Graph

12 Commits (c871a3a9ee3163839576ec9961cb2d0bbae1bcb8)

Author SHA1 Message Date
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
2021-01-20 01:02:56 +02:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
Istvan Csomortani a39fa831d0 ad9371:a10gx: Relax interconnect requirements 2020-08-11 10:14:18 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
Laszlo Nagy b98eb28dca adrv9371: update adcfifo/dacfifo 2019-01-23 14:45:45 +02:00
Adrian Costina 37323e3444 adrv9371x: A10GX, added extra pipelining in the interconnect in order to improve timing 2017-10-20 13:46:22 +01:00
Rejeesh Kutty 4f0accbbfa adrv9371x fix dacfifo name 2017-05-18 12:54:14 -04:00
Rejeesh Kutty ec89b1a45f altera/adrv9371x- add dacfifo 2017-03-01 15:52:07 -05:00
Rejeesh Kutty 4a783d523d projects/altera* - default & common qsys commands 2016-12-20 16:27:44 -05:00
Adrian Costina 500d8bfb90 adrv9371x: A10GX, fix makefile and system_qsys.tcl script 2016-09-21 18:11:35 +03:00
Adrian Costina eb55f600fb adrv9371x: Initial commit
-need to fix dc filter module for AD9371 / altera
2016-08-16 15:50:46 +03:00