Commit Graph

3794 Commits (c728299e71f0a1953cfb7b279c42fa3597c24e41)

Author SHA1 Message Date
Lars-Peter Clausen 495d2f3056 axi_dmac: Propagate awlen/arlen width through the core
Depending on whether the core is configured for AXI4 or AXI3 mode the width
of the awlen/arlen signal is either 8 or 4 bit. At the moment this is only
considered in top-level module and all other modules use 8 bit internally.
This causes warnings about truncated signals in AXI3 mode, to resolve this
forward the width of the signal through the core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 17:19:38 +02:00
Istvan Csomortani ebfed4b24b ad_axi_ip_constr.xdc: Delete file 2017-03-30 16:16:02 +03:00
Istvan Csomortani 873fbfd6d7 library: Update scripts with new constraints
Update all IPs tcl scripts with the new constraints files.
Refer to commit 335fef0.
2017-03-30 16:16:02 +03:00
Istvan Csomortani 31a5c674f2 fmcomms2: Update constraints file paths 2017-03-30 16:16:02 +03:00
Istvan Csomortani 8ba6012b6b restructure: Move xilinx specific constraints to /library/xilinx/common/ 2017-03-30 16:16:02 +03:00
Lars-Peter Clausen 983e56d72c ad9963: Remove localparams from module parameter list
Declaring local parameters in the module parameter list is not valid
verilog. For some reasons Vivado accepts it nevertheless so the code has
worked so far. But this is not true for other tools, so move the local
parameter definitions inside the module body.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:40:28 +02:00
Lars-Peter Clausen e04793b6eb m2k: standalone: Assign 0 to unused GPIO inputs
To avoid warnings from the tools assign 0 to the unused GPIO inputs.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-30 11:16:25 +02:00
Rejeesh Kutty 8eb1dd0a8b adrv9371x/altera- xilinx/chip-select consistency 2017-03-29 12:59:09 -04:00
Istvan Csomortani 1d448f0013 adi_ip: Set up SCOPE_TO_REF for xdc and save the core 2017-03-29 18:40:24 +03:00
Istvan Csomortani ea7e93d27f fmcomms2: Use the new constriants from 335fef0 2017-03-29 18:36:09 +03:00
Istvan Csomortani 335fef0f42 ad_axi_ip_constr: Split up this constraint file into separate files
For experimentation, to solve a constraint scoping issue, split up the
ad_axi_ip_constraint file into separate constraints file, in function
of there parent module.
2017-03-29 18:31:40 +03:00
Lars-Peter Clausen 24a7d8ea9d m2k: Remove redundant s_axi_{aclk,aresetn} assignment
ad_cpu_interconnect will make sure to connect the clock and the reset of
the AXI interface. Remove the redundant manual assignments.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-28 11:14:48 +02:00
Rejeesh Kutty deb8635854 adrv9371x/altera- gpio equivalency fix 2017-03-27 16:37:55 -04:00
Rejeesh Kutty 8f1564a9c4 adrv9371x/a10gx- gpio matching 2017-03-27 13:51:45 -04:00
Rejeesh Kutty 2419b3626b ad9684- fix sdc typo 2017-03-23 12:49:44 -04:00
Rejeesh Kutty ae0f4672b2 daq1/a10gx- fix project to compile 2017-03-23 09:46:40 -04:00
Rejeesh Kutty cc6bf53d98 adrv9371x/a10soc- altera reset synchronizer false path? 2017-03-23 09:46:40 -04:00
Adrian Costina 968d94603e fmcjesdadc1: Update xcvr configuration to the default one used for this board 2017-03-23 11:31:00 +02:00
Rejeesh Kutty 4a275302a0 a5soc- add ddr3 location assignments 2017-03-22 10:12:34 -04:00
Rejeesh Kutty 7e87ecae22 altera/a10gx- daq1/fmcomms2 fix typos 2017-03-22 09:48:02 -04:00
Rejeesh Kutty b3f06af77a altera srf files do not work 2017-03-22 09:25:50 -04:00
Rejeesh Kutty 66a5d44a18 a5gte- add constraints for tq 2017-03-21 10:53:31 -04:00
Rejeesh Kutty 2e22ce3b62 a10gx- ignore preliminary timing model warnings 2017-03-21 10:52:28 -04:00
Rejeesh Kutty d84e34fe5f arradio/c5soc- reset false path for vga dma 2017-03-21 10:15:38 -04:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Rejeesh Kutty c7351f3ce3 arradio/c5soc- remove qsys files 2017-03-20 15:56:07 -04:00
Rejeesh Kutty 589e6b53d8 arradio/c5soc- qsys-script flow 2017-03-20 15:42:33 -04:00
Rejeesh Kutty b39fecadd9 altera- ignore preliminary timing messages 2017-03-20 12:48:53 -04:00
Rejeesh Kutty 7dfa8c599f arradio/c5soc- updated to new framework/16.0 2017-03-20 12:15:18 -04:00
Rejeesh Kutty 12f44ccbcc arradio/c5soc- critical warnings fix 2017-03-20 12:14:21 -04:00
Rejeesh Kutty c277b39796 arradio/c5soc- critical warnings fix 2017-03-20 12:14:13 -04:00
Rejeesh Kutty 9b6dd27c23 ad9361- delay initialization 2017-03-15 12:06:59 -04:00
Adrian Costina 09bcecb6ed m2k: Simplify DMA connection to HP1 2017-03-15 15:11:30 +02:00
Adrian Costina cd0701513a axi_logic_analyzer: Added an additional delay to the trigger, to be similar with the analog path 2017-03-14 18:00:42 +02:00
Lars-Peter Clausen 3c7f73a880 axi_dmac: Fix dummy port enablement dependency
It seems that in the latest version a constant of "0" is no longer a valid
enablement dependency and "false" has be used instead.

Not setting the enablement dependency correctly results in the AXI port to
be assumed to be read-write rather than just read or write. This will
generate unnecessary logic for example in interconnects to which the DMA
controller is connected.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-03-14 16:03:25 +01:00
Adrian Costina d7edd71aef axi_logic_analyzer: Triggering changes on valid data 2017-03-14 15:25:00 +02:00
Adrian Costina 2a9b3cea09 m2k: Changed the way DMAs connect to the PS7 DDR, to optimize resources use 2017-03-14 13:57:50 +02:00
Adrian Costina f7c2bd943b m2k: Enable AD9963 adc data path processing.
- part of the path is the sign extension module. Without it, the triggering doesn't work correctly
2017-03-13 23:18:29 +02:00
Rejeesh Kutty c3c8c366d3 axi_ad9361- add receive init delay 2017-03-13 16:28:53 -04:00
Rejeesh Kutty 1ef064ac03 axi_ad9361- add receive init delay 2017-03-13 16:28:38 -04:00
Rejeesh Kutty b0e88eb5ff axi_ad9361- add receive init delay 2017-03-13 16:28:24 -04:00
Rejeesh Kutty dac75f79ab fmcomms5/usrpe31x- add iodelay report 2017-03-10 13:38:27 -05:00
Rejeesh Kutty 1b3f752c3d pzsdr1/pzsdr2/pluto- add iodelay report 2017-03-10 12:55:22 -05:00
Rejeesh Kutty 0ae79ca7ac move/rename - delay script belongs to ad9361 2017-03-10 12:44:32 -05:00
AndreiGrozav e736504e0f fmcjesdadc1, usdrx1: Using the same clock in rx_data path 2017-03-10 14:26:51 +02:00
AndreiGrozav d08d1d5a1b adrv9371x ,daq3, fmcomms7, fmcomms11: add dac_fifo missing reset connection 2017-03-10 14:20:42 +02:00
Rejeesh Kutty 452e5e5ce0 fmcomms2- add delay reporting for iodelay 2017-03-09 15:29:15 -05:00
Rejeesh Kutty 8bdfbe2b0a fmcomms2- report delays 2017-03-09 15:21:42 -05:00
Adrian Costina ce6b0cc7f3 util_fir_dec: Changed output rounding mode to Symmetric rounding to Zero
This removes the added DC component that was introduced by the previous rounding mode
2017-03-09 16:33:17 +02:00
AndreiGrozav 7e5d8664ad fmcjesdadc1_a5gt: rx_data pins are all associated to the same clock 2017-03-09 08:57:03 +02:00